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21ca72a7d0
@ -126,7 +126,7 @@ module fround import cvw::*; #(parameter cvw_t P) (
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3'b001: RoundUp = 0; // RZ
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3'b010: RoundUp = Xs & (Rp | Tp); // RN
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3'b011: RoundUp = ~Xs & (Rp | Tp); // RP
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3'b101: RoundUp = Rp; // RNTA
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3'b100: RoundUp = Rp; // RNTA
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default: RoundUp = 0; // should never happen
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endcase
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