diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv index 20114b15a..7019675e7 100644 --- a/pipelined/src/privileged/csr.sv +++ b/pipelined/src/privileged/csr.sv @@ -40,7 +40,7 @@ module csr #(parameter input logic FlushE, FlushM, FlushW, input logic StallE, StallM, StallW, input logic [31:0] InstrM, - input logic [`XLEN-1:0] PCM, SrcAM, + input logic [`XLEN-1:0] PCM, SrcAM, IEUAdrM, input logic CSRReadM, CSRWriteM, TrapM, MTrapM, STrapM, mretM, sretM, wfiM, InterruptM, input logic MTimerInt, MExtInt, SExtInt, MSwInt, input logic [63:0] MTIME_CLINT, @@ -55,7 +55,7 @@ module csr #(parameter input logic ICacheMiss, input logic ICacheAccess, input logic [1:0] NextPrivilegeModeM, PrivilegeModeW, - input logic [`XLEN-1:0] CauseM, NextFaultMtvalM, + input logic [`XLEN-1:0] CauseM, //NextFaultMtvalM, input logic SelHPTW, output logic [1:0] STATUS_MPP, output logic STATUS_SPP, STATUS_TSR, STATUS_TVM, @@ -71,7 +71,7 @@ module csr #(parameter input logic [4:0] SetFflagsM, output logic [2:0] FRM_REGW, - output logic [`XLEN-1:0] CSRReadValW, + output logic [`XLEN-1:0] CSRReadValW, PrivilegedNextPCM, output logic IllegalCSRAccessM, BigEndianM ); @@ -96,10 +96,57 @@ module csr #(parameter logic IllegalCSRMWriteReadonlyM; logic [`XLEN-1:0] CSRReadVal2M; logic [11:0] MIP_REGW_writeable; + logic [`XLEN-1:0] PrivilegedTrapVector, PrivilegedVectoredTrapVector, NextFaultMtvalM; + logic InstrValidNotFlushedM; assign InstrValidNotFlushedM = ~StallW & ~FlushW; + /////////////////////////////////////////// + // MTVAL + /////////////////////////////////////////// + + always_comb + case (CauseM) + 12, 1, 3: NextFaultMtvalM = PCM; // Instruction page/access faults, breakpoint + 2: NextFaultMtvalM = {{(`XLEN-32){1'b0}}, InstrM}; // Illegal instruction fault + 0, 4, 6, 13, 15, 5, 7: NextFaultMtvalM = IEUAdrM; // Instruction misaligned, Load/Store Misaligned/page/access faults + default: NextFaultMtvalM = 0; // Ecall, interrupts + endcase + + + /////////////////////////////////////////// + // Trap Vectoring + /////////////////////////////////////////// + // + // POSSIBLE OPTIMIZATION: + // From 20190608 privielegd spec page 27 (3.1.7) + // > Allowing coarser alignments in Vectored mode enables vectoring to be + // > implemented without a hardware adder circuit. + // For example, we could require m/stvec be aligned on 7 bits to let us replace the adder directly below with + // [untested] PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:7], CauseM[3:0], 4'b0000} + // However, this is program dependent, so not implemented at this time. + + always_comb + if (NextPrivilegeModeM == `S_MODE) PrivilegedTrapVector = STVEC_REGW; + else PrivilegedTrapVector = MTVEC_REGW; + + if(`VECTORED_INTERRUPTS_SUPPORTED) begin:vec + always_comb + if (PrivilegedTrapVector[1:0] == 2'b01 & CauseM[`XLEN-1] == 1) + PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2] + CauseM[`XLEN-3:0], 2'b00}; + else + PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2], 2'b00}; + end + else begin + assign PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2], 2'b00}; + end + + always_comb + if (TrapM) PrivilegedNextPCM = PrivilegedVectoredTrapVector; + else if (mretM) PrivilegedNextPCM = MEPC_REGW; + else PrivilegedNextPCM = SEPC_REGW; + // modify CSRs always_comb begin // Choose either rs1 or uimm[4:0] as source diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv index a0ea3ef65..62924d899 100644 --- a/pipelined/src/privileged/privileged.sv +++ b/pipelined/src/privileged/privileged.sv @@ -81,7 +81,7 @@ module privileged ( output logic BreakpointFaultM, EcallFaultM, wfiM, IntPendingM, BigEndianM ); - logic [`XLEN-1:0] CauseM, NextFaultMtvalM; + logic [`XLEN-1:0] CauseM; //, NextFaultMtvalM; logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, STVEC_REGW, MTVEC_REGW; logic [`XLEN-1:0] MEDELEG_REGW; logic [11:0] MIDELEG_REGW; @@ -125,7 +125,7 @@ module privileged ( csr csr(.clk, .reset, .FlushE, .FlushM, .FlushW, .StallE, .StallM, .StallW, - .InstrM, .PCM, .SrcAM, + .InstrM, .PCM, .SrcAM, .IEUAdrM, .CSRReadM, .CSRWriteM, .TrapM, .MTrapM, .STrapM, .mretM, .sretM, .wfiM, .InterruptM, .MTimerInt, .MExtInt, .SExtInt, .MSwInt, .MTIME_CLINT, @@ -133,7 +133,7 @@ module privileged ( .BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .NextPrivilegeModeM, .PrivilegeModeW, - .CauseM, .NextFaultMtvalM, .SelHPTW, + .CauseM, /*.NextFaultMtvalM,*/ .SelHPTW, .STATUS_MPP, .STATUS_SPP, .STATUS_TSR, .STATUS_TVM, .MEPC_REGW, .SEPC_REGW, .STVEC_REGW, .MTVEC_REGW, @@ -146,7 +146,7 @@ module privileged ( .PMPADDR_ARRAY_REGW, .SetFflagsM, .FRM_REGW, - .CSRReadValW, + .CSRReadValW,.PrivilegedNextPCM, .IllegalCSRAccessM, .BigEndianM); privpiperegs ppr(.clk, .reset, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, @@ -164,11 +164,11 @@ module privileged ( .MEPC_REGW, .SEPC_REGW, .STVEC_REGW, .MTVEC_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW, .STATUS_MIE, .STATUS_SIE, - .PCM, .IEUAdrM, .InstrM, + /* .PCM, .IEUAdrM, .InstrM,*/ .InstrValidM, .CommittedM, .TrapM, .MTrapM, .STrapM, .RetM, .InterruptM, .IntPendingM, - .PrivilegedNextPCM, .CauseM, .NextFaultMtvalM); + /* .PrivilegedNextPCM, */.CauseM/*MtvalM*/); endmodule diff --git a/pipelined/src/privileged/trap.sv b/pipelined/src/privileged/trap.sv index 176292f68..cf26a6433 100644 --- a/pipelined/src/privileged/trap.sv +++ b/pipelined/src/privileged/trap.sv @@ -42,13 +42,13 @@ module trap ( (* mark_debug = "true" *) input logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, STVEC_REGW, MTVEC_REGW, (* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW, input logic STATUS_MIE, STATUS_SIE, - input logic [`XLEN-1:0] PCM, - input logic [`XLEN-1:0] IEUAdrM, - input logic [31:0] InstrM, +/* input logic [`XLEN-1:0] PCM, + input logic [`XLEN-1:0] IEUAdrM, + input logic [31:0] InstrM, */ input logic InstrValidM, CommittedM, output logic TrapM, MTrapM, STrapM, RetM, output logic InterruptM, IntPendingM, - output logic [`XLEN-1:0] PrivilegedNextPCM, CauseM, NextFaultMtvalM + output logic [`XLEN-1:0] /*PrivilegedNextPCM, */CauseM //NextFaultMtvalM // output logic [11:0] MIP_REGW, SIP_REGW, UIP_REGW, MIE_REGW, SIE_REGW, UIE_REGW, // input logic WriteMIPM, WriteSIPM, WriteUIPM, WriteMIEM, WriteSIEM, WriteUIEM ); @@ -57,7 +57,7 @@ module trap ( logic ExceptionM; (* mark_debug = "true" *) logic [11:0] PendingIntsM, ValidIntsM; //logic InterruptM; - logic [`XLEN-1:0] PrivilegedTrapVector, PrivilegedVectoredTrapVector; + //logic [`XLEN-1:0] PrivilegedTrapVector, PrivilegedVectoredTrapVector; /////////////////////////////////////////// // Determine pending enabled interrupts @@ -87,6 +87,7 @@ module trap ( assign STrapM = TrapM & (NextPrivilegeModeM == `S_MODE) & `S_SUPPORTED; assign RetM = mretM | sretM; +/* always_comb if (NextPrivilegeModeM == `S_MODE) PrivilegedTrapVector = STVEC_REGW; else PrivilegedTrapVector = MTVEC_REGW; @@ -118,6 +119,7 @@ module trap ( if (TrapM) PrivilegedNextPCM = PrivilegedVectoredTrapVector; else if (mretM) PrivilegedNextPCM = MEPC_REGW; else PrivilegedNextPCM = SEPC_REGW; + */ /////////////////////////////////////////// // Cause priority defined in table 3.7 of 20190608 privileged spec @@ -145,17 +147,6 @@ module trap ( else if (StoreAmoAccessFaultM) CauseM = 7; else CauseM = 0; - /////////////////////////////////////////// - // MTVAL - /////////////////////////////////////////// - - always_comb - case (CauseM) - 12, 1, 3: NextFaultMtvalM = PCM; // Instruction page/access faults, breakpoint - 2: NextFaultMtvalM = {{(`XLEN-32){1'b0}}, InstrM}; // Illegal instruction fault - 0, 4, 6, 13, 15, 5, 7: NextFaultMtvalM = IEUAdrM; // Instruction misaligned, Load/Store Misaligned/page/access faults - default: NextFaultMtvalM = 0; // Ecall, interrupts - endcase /* always_comb if (InstrPageFaultM) NextFaultMtvalM = PCM; else if (InstrAccessFaultM) NextFaultMtvalM = PCM;