mirror of
https://github.com/openhwgroup/cvw
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adding PIPELINE tests
This commit is contained in:
Shriya Nadgauda
parent
51291949d8
commit
21989ee615
635
wally-pipelined/testgen/testgen-PIPELINE.py
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635
wally-pipelined/testgen/testgen-PIPELINE.py
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import numpy as np
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import string
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from datetime import datetime
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INSTRUCTION_SIZE = 32
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VALID_REGISTERS = [str(x) for x in range(1, 32) if x != 6] # generates list of ints from (1, 31) without 6
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# Enumeration for decoding instruction formats
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NAME = 0
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REG = 1
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ADDR = 5
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IMM = 6
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ZIMM = 7
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LABEL = 8
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# Enumeration for decoding alignments
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BYTE = 1
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HALF = INSTRUCTION_SIZE // 16
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WORD = INSTRUCTION_SIZE // 8
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NONE = 1
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wordsize = 8
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class InstrGenerator():
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class InstrDict():
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INSTR_RV32I = \
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["lb", "lh", "lw", "lbu", "lhu", "addi", "slli", "slti", "sltiu", "xori", \
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"srli", "srai", "ori", "andi", "auipc", "sb", "sh", "sw", "add", "sub", \
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"sll", "slt", "sltu", "xor", "srl", "sra", "or", "and", "lui", "beq", \
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"bne", "blt", "bge", "bltu", "bgeu", "jal"] #37 #"jalr"
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INSTR_RV64M = ["mul", "mulh", "muhsu", "mulhu"] #"div", "divu", "rem", "remu"
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#TODO: Add jalr functionality
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# Lists of instructions that follow a specific format
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INSTR_MEM = ["lb", "lh", "lw", "lbu", "lhu", "sb", "sh", "sw"] #8
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INSTR_DEST_SRC1_IMM = ["addi", "slti", "sltiu", "xori", "ori", "andi", "jarl"] #7
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INSTR_DEST_SRC1_ZIMM = ["slli", "srli", "srai"] #3
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INSTR_DEST_IMM = ["auipc", "lui"] #2
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INSTR_DEST_SRC1_SRC2 = ["add", "sub", "sll", "slt", "sltu", "xor", "srl", "sra", "or", "and"]
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INSTR_SRC1_SRC2_LABEL = ["beq", "bne", "blt", "bge", "bltu", "bgeu"] #6
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INSTR_DEST_LABEL = ["jal"] #1
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INSTR_DEST_SRC1_SRC2_64M = ["mul", "mulh", "muhsu", "mulhu", "div", "divu", "rem", "remu"]
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def __init__(self):
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self.instr = {}
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def fillInstructionDictRV32i(self):
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self.instr["lb"] = [(NAME, REG, ADDR), BYTE]
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self.instr["lh"] = [(NAME, REG, ADDR), HALF]
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self.instr["lw"] = [(NAME, REG, ADDR), WORD]
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self.instr["lbu"] = [(NAME, REG, ADDR), BYTE]
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self.instr["lhu"] = [(NAME, REG, ADDR), HALF]
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self.instr["addi"] = [(NAME, REG, REG, IMM), NONE]
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self.instr["slli"] = [(NAME, REG, REG, ZIMM), NONE]
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self.instr["slti"] = [(NAME, REG, REG, IMM), NONE]
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self.instr["sltiu"] = [(NAME, REG, REG, IMM), NONE]
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self.instr["xori"] = [(NAME, REG, REG, IMM), NONE]
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self.instr["srli"] = [(NAME, REG, REG, ZIMM), NONE]
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self.instr["srai"] = [(NAME, REG, REG, ZIMM), NONE]
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self.instr["ori"] = [(NAME, REG, REG, IMM), NONE]
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self.instr["andi"] = [(NAME, REG, REG, IMM), NONE]
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self.instr["auipc"] = [(NAME, REG, IMM), NONE]
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self.instr["sb"] = [(NAME, REG, ADDR), BYTE]
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self.instr["sh"] = [(NAME, REG, ADDR), HALF]
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self.instr["sw"] = [(NAME, REG, ADDR), WORD]
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self.instr["add"] = [(NAME, REG, REG, REG), NONE]
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self.instr["sub"] = [(NAME, REG, REG, REG), NONE]
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self.instr["sll"] = [(NAME, REG, REG, REG), NONE]
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self.instr["slt"] = [(NAME, REG, REG, REG), NONE]
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self.instr["sltu"] = [(NAME, REG, REG, REG), NONE]
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self.instr["xor"] = [(NAME, REG, REG, REG), NONE]
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self.instr["srl"] = [(NAME, REG, REG, REG), NONE]
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self.instr["sra"] = [(NAME, REG, REG, REG), NONE]
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self.instr["or"] = [(NAME, REG, REG, REG), NONE]
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self.instr["and"] = [(NAME, REG, REG, REG), NONE]
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self.instr["lui"] = [(NAME, REG, IMM), NONE]
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self.instr["beq"] = [(NAME, REG, REG, LABEL), NONE]
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self.instr["bne"] = [(NAME, REG, REG, LABEL), NONE]
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self.instr["blt"] = [(NAME, REG, REG, LABEL), NONE]
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self.instr["bge"] = [(NAME, REG, REG, LABEL), NONE]
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self.instr["bltu"] = [(NAME, REG, REG, LABEL), NONE]
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self.instr["bgeu"] = [(NAME, REG, REG, LABEL), NONE]
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#self.instr["jalr"] = [(NAME, REG, REG, IMM), NONE]
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self.instr["jal"] = [(NAME, REG, LABEL), WORD]
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def fillInstructionDictRV64M(self):
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self.instr["mul"] = [(NAME, REG, REG, REG), NONE]
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self.instr["mulh"] = [(NAME, REG, REG, REG), NONE]
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self.instr["mulhsu"] = [(NAME, REG, REG, REG), NONE]
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self.instr["mulhu"] = [(NAME, REG, REG, REG), NONE]
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self.instr["div"] = [(NAME, REG, REG, REG), NONE]
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self.instr["divu"] = [(NAME, REG, REG, REG), NONE]
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self.instr["rem"] = [(NAME, REG, REG, REG), NONE]
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self.instr["remu"] = [(NAME, REG, REG, REG), NONE]
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class RandomSelect():
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LETTER_CHOICES = string.ascii_letters
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def randReg(self, regs):
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return regs[np.random.randint(0, len(regs))]
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def randBinary(self, signed, numBits, valueAlignment):
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# use this for corners: xlen = 32 here
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corners = [0, 1, 2, 0xFF, 0x624B3E976C52DD14 % 2**numBits, 2**(numBits-1)-2, 2**(numBits-1)-1, \
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2**(numBits-1), 2**(numBits-1)+1, 0xC365DDEB9173AB42 % 2**numBits, 2**(numBits)-2, 2**(numBits)-1]
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# when not biased don't gen numbers from (|2^(n-2) to 2^(n-2)|)
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biased = np.random.randint(0, 3) # on 2 generate random edge case
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returnVal = 0
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sign = 0
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if biased < 2:
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# print("unbiased")
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if not(signed):
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returnVal = np.random.randint(0, 2**(numBits) - 1)
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else:
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returnVal = np.random.randint(-2**(numBits - 1), 2**(numBits - 1) - 1)
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else:
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# print("corner")
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returnVal = corners[np.random.randint(0, len(corners))]
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binReturnVal = bin(returnVal)
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if returnVal >= 0:
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binReturnVal = binReturnVal[2:] # get rid of 0b
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#make binary correct length
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while(len(binReturnVal) < numBits):
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binReturnVal = "0" + binReturnVal
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else:
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binReturnVal = binReturnVal[3:] # get rid of -0b
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#two's compliment
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flipped = ''.join('1' if x == '0' else '0' for x in binReturnVal)
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added = bin(int(flipped, 2) + 1)[2:]
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while(len(added) < len(flipped)):
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added = "0" + added
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while(len(added) < numBits):
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added = "1" + added
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binReturnVal = added
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# ensure correct value assignment
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if valueAlignment == 1:
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return binReturnVal
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indexVal = valueAlignment // 2
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returnValue = binReturnVal[:-indexVal] + "0"*indexVal
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return returnValue
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def randHex(self, sign, numBits, divisibleByValue):
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return hex(int(self.randBinary(sign, numBits*4, divisibleByValue), 2))
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def randDec(self, valueRangeMin, valueRangeMax, divisibleByValue):
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valRange = (valueRangeMax - valueRangeMin)//divisibleByValue
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return (np.random.randint(0, valRange + 1) * divisibleByValue + valueRangeMin)
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def __init__(self, numMemoryRegisters, xlen):
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self.instrDict = self.InstrDict()
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self.instrDict.fillInstructionDictRV32i()
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if (xlen == 64):
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self.instrDict.fillInstructionDictRV64M()
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self.randSelect = self.RandomSelect()
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self.memoryAdrList = []
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self.populateMemory()
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self.prevLabel = 0
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self.memReg = []
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self.anyReg = VALID_REGISTERS[:]
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self.xlen = xlen
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self.test_count = 0
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for i in range(0, numMemoryRegisters):
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reg = self.randSelect.randReg(self.anyReg)
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self.anyReg.remove(reg)
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self.memReg.append(reg)
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self.PC = int("80000108",16)
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def addPC(self, instr): #adapted from BB code
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if instr == "li":
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self.PC += 8 if (self.xlen == 32) else 20
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elif instr == "la":
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self.PC += 8
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else:
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self.PC += 4
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def getRandInstruction(self, instr):
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return instr[np.random.randint(0, len(instr))]
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def getForwardingInstructions(self, instr): #TODO make so that memory register can be manipulated
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fields, alignment = self.instrDict.instr[instr]
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ld_instr = "lw"
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num = np.random.randint(0, 2) # 0 signed, on 1 unsigned
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if alignment == BYTE:
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if num == 0:
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ld_instr = "lbu"
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else:
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ld_instr = "lb"
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if alignment == HALF:
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if num == 0:
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ld_instr = "lhu"
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else:
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ld_instr = "lw"
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reg1 = self.randSelect.randReg(self.anyReg)
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mask = self.randSelect.randHex(True, 3, alignment)
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reg_set_instr = "andi x" + reg1 + ", x" + reg1 + ", SEXT_IMM(" + mask + ")" # set register to multiple of 4
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rd = self.randSelect.randReg(self.anyReg)
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imm1 = self.memoryAdrList[np.random.randint(0, len(self.memoryAdrList))] #load imm
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mem_instr_ld = ld_instr + " x" + rd + ", " + imm1 + "(x" + reg1 + ")" #load value to rd
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reg2 = self.randSelect.randReg(self.memReg)
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imm2 = self.memoryAdrList[np.random.randint(0, len(self.memoryAdrList))] #str imm
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mem_instr_str = "sw" + " x" + rd + ", " + imm2 + "(x" + reg2 + ")" #store value of rd
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instructions = [reg_set_instr, mem_instr_ld, mem_instr_str]
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check_instr = self.genTestInstr(rd)
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for check in check_instr:
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instructions.append(check)
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return instructions
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def jumpInstruction(self, instr):
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fields, alignment = self.instrDict.instr[instr]
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# randomly determine forward or back branch direction
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fwd = np.random.randint(0, 2) #fwd on 1, bwd on 0
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taken = np.random.randint(0,2) #not taken on 0, taken on 1
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reg_pc = self.randSelect.randReg(self.anyReg)
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instructions = []
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if fwd == 1:
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instructions.append(instr + " x" + reg_pc + ", " + str(self.prevLabel) + "f")
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numInstr = np.random.randint(0, 6)
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# add random alu instructions after jumping before jump point
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reg_check = 1
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for i in range(0, numInstr):
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curr = self.getRandInstruction(self.instrDict.INSTR_DEST_SRC1_SRC2)
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rd = self.randSelect.randReg(self.anyReg)
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while (rd == reg_pc):
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rd = self.randSelect.randReg(self.anyReg)
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reg_check = rd
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r1 = self.randSelect.randReg(self.anyReg)
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r2 = self.randSelect.randReg(self.anyReg)
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instructions.append(curr + " x" + rd + ", x" + r1 + ", x" + r2)
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instructions.append(str(self.prevLabel) + ":")
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self.prevLabel += 1
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#make sure jump was taken
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check_instr = self.genTestInstr(reg_check)
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for check in check_instr:
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instructions.append(check)
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#check value in pc + 4 reg
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check_instr = self.genTestInstr(reg_pc)
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for check in check_instr:
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instructions.append(check)
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else:
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reg1 = self.randSelect.randReg(self.anyReg)
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reg2 = self.randSelect.randReg(self.anyReg)
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while reg2 == reg1:
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reg2 = self.randSelect.randReg(self.anyReg)
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instructions.append("jal x" + reg1 + ", 1f")
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instructions.append("2:")
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instructions.append("jal x" + reg2 + ", 3f")
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instructions.append("1:")
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numInstr = np.random.randint(0,6)
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for i in range(0, numInstr):
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curr = self.getRandInstruction(self.instrDict.INSTR_DEST_SRC1_SRC2)
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rd = self.randSelect.randReg(self.anyReg)
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r1 = self.randSelect.randReg(self.anyReg)
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r2 = self.randSelect.randReg(self.anyReg)
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instructions.append(curr + " x" + rd + ", x" + r1 + ", x" + r2)
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#test case here
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instructions.append("jal x" + reg2 + ", 2b")
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instructions.append("3:")
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check_instr = self.genTestInstr(reg1)
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for check in check_instr:
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instructions.append(check)
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# jump to 1
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# #2
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# jump to 3
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# #1
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# junk here
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# test: jump to 2
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# #3
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# check answer from 1
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return instructions
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def branchInstruction(self, instr):
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fields, alignment = self.instrDict.instr[instr]
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# randomly determine forward or back branch direction
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fwd = np.random.randint(0, 2) #fwd on 1, bwd on 0
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taken = np.random.randint(0,2) #not taken on 0, taken on 1
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instructions = []
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# pick 2 registers for branch comparison
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reg1 = self.randSelect.randReg(self.anyReg)
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reg2 = reg1
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while (reg2 == reg1):
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reg2 = self.randSelect.randReg(self.anyReg)
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if (fwd == 1):
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# set r1 and r2 to what they should be to do the branching we want
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#TODO this assumed that greater than equal to or lteq are instead jsut equal, will be changed later
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if (instr == "beq" and taken==1) or (instr == "bne" and taken==0) or \
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(instr == "blt" and taken==0) or (instr == "bge" and taken==1) or \
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||||||
|
(instr == "bltu" and taken==0) or (instr == "bgeu" and taken==1): #r1 = r2
|
||||||
|
instructions.append("mv x" + reg1 + ", x" + reg2)
|
||||||
|
|
||||||
|
elif (instr == "beq" and taken==0) or (instr == "bne" and taken==1) or \
|
||||||
|
(instr == "blt" and taken==1) or (instr == "bltu" and taken==1): #r2 = r1 + 1
|
||||||
|
instructions.append("addi x" + reg2 + ", x" + reg1 + ", 1")
|
||||||
|
|
||||||
|
else:
|
||||||
|
instructions.append("addi x" + reg2 + ", x" + reg1 + ", -1") #r2 = r1 - 1
|
||||||
|
|
||||||
|
# add branching instruction
|
||||||
|
instructions.append(instr + " x" + reg1 + ", x" + reg2 + ", " + str(self.prevLabel) + "f")
|
||||||
|
numInstr = np.random.randint(0, 6)
|
||||||
|
# add random alu instructions after branching before branch point
|
||||||
|
reg_check = 1
|
||||||
|
for i in range(0, numInstr):
|
||||||
|
curr = self.getRandInstruction(self.instrDict.INSTR_DEST_SRC1_SRC2)
|
||||||
|
rd = self.randSelect.randReg(self.anyReg)
|
||||||
|
reg_check = rd
|
||||||
|
r1 = self.randSelect.randReg(self.anyReg)
|
||||||
|
r2 = self.randSelect.randReg(self.anyReg)
|
||||||
|
instructions.append(curr + " x" + rd + ", x" + r1 + ", x" + r2)
|
||||||
|
instructions.append(str(self.prevLabel) + ":")
|
||||||
|
self.prevLabel += 1
|
||||||
|
check_instr = self.genTestInstr(reg_check)
|
||||||
|
for check in check_instr:
|
||||||
|
instructions.append(check)
|
||||||
|
return instructions
|
||||||
|
|
||||||
|
# Backwards branch case
|
||||||
|
else:
|
||||||
|
if (not taken):
|
||||||
|
if instr == "beq":
|
||||||
|
randImm = self.randSelect.randHex(True, 1, 1)
|
||||||
|
while randImm == "0x0":
|
||||||
|
randImm = self.randSelect.randHex(True, 1, 1)
|
||||||
|
instructions.append("addi x" + reg2 + ", x" + reg1 + ", MASK_XLEN(" + str(randImm) + ")") #r2 = r1 + randImm (-10, 10) and not 0
|
||||||
|
|
||||||
|
elif instr == "bne":
|
||||||
|
instructions.append("addi x" + reg2 + ", x" + reg1 + ", 0") #r2 = r1 + 0
|
||||||
|
|
||||||
|
elif instr == "bltu" or instr == "blt":
|
||||||
|
randImm = np.random.randint(-10, 0)
|
||||||
|
randMaskLen = np.random.randint(10, 100)
|
||||||
|
instructions.append("addi x" + reg1 + ", x0, " + "MASK_XLEN(" + str(randMaskLen) + ")") # set reg1 to be rand positive number, helps stop infinite looping
|
||||||
|
instructions.append("addi x" + reg2 + ", x" + reg1 + ", MASK_XLEN(" + str(randImm) + ")") #r2 = r1 + randImm (-10, -1)
|
||||||
|
|
||||||
|
elif instr == "bgeu" or instr == "bge":
|
||||||
|
randImm = np.random.randint(1, 11)
|
||||||
|
randMaskLen = np.random.randint(10, 100)
|
||||||
|
instructions.append("addi x" + reg1 + ", x0, "+ "MASK_XLEN(" + str(randMaskLen) + ")") # set reg1 to be rand positive number, helps stop infinite looping
|
||||||
|
instructions.append("addi x" + reg2 + ", x" + reg1 + ", MASK_XLEN(" + str(randImm) + ")") #r2 = r1 + randImm (1, 11)
|
||||||
|
|
||||||
|
instructions.append(str(self.prevLabel) + ":")
|
||||||
|
numInstr = np.random.randint(0, 6)
|
||||||
|
# add random alu instructions after branching before branch point
|
||||||
|
reg_check = 1
|
||||||
|
for i in range(0, numInstr):
|
||||||
|
curr = self.getRandInstruction(self.instrDict.INSTR_DEST_SRC1_SRC2)
|
||||||
|
rd = self.randSelect.randReg(self.anyReg)
|
||||||
|
reg_check = rd
|
||||||
|
while rd == reg1 or rd==reg2:
|
||||||
|
rd = self.randSelect.randReg(self.anyReg)
|
||||||
|
r1 = self.randSelect.randReg(self.anyReg)
|
||||||
|
r2 = self.randSelect.randReg(self.anyReg)
|
||||||
|
instructions.append(curr + " x" + rd + ", x" + r1 + ", x" + r2)
|
||||||
|
|
||||||
|
check_instr = self.genTestInstr(reg_check)
|
||||||
|
for check in check_instr:
|
||||||
|
instructions.append(check)
|
||||||
|
|
||||||
|
else:
|
||||||
|
#setup reg instructions before any branching stuff
|
||||||
|
if instr == "beq":
|
||||||
|
numTimesRepeat = 1 #can only be repeated once with the way we are doing this
|
||||||
|
instructions.append("addi x" + reg2 + ", x" + reg1 + ", MASK_XLEN(" + str(numTimesRepeat) + ")") #r2 = r1 + numTimesRepeat ( - 6)
|
||||||
|
instructions.append(str(self.prevLabel) + ":")
|
||||||
|
instructions.append("addi x" + reg2 + ", x" + reg2 + ", -1")
|
||||||
|
|
||||||
|
elif instr == "bne":
|
||||||
|
numTimesRepeat = np.random.randint(2, 6)
|
||||||
|
instructions.append("addi x" + reg2 + ", x" + reg1 + ", MASK_XLEN(" + str(numTimesRepeat) + ")") #r2 = r1 + numTimesRepeat (2 - 6)
|
||||||
|
instructions.append(str(self.prevLabel) + ":")
|
||||||
|
instructions.append("addi x" + reg2 + ", x" + reg2 + ", -1")
|
||||||
|
|
||||||
|
elif instr == "bltu":
|
||||||
|
numTimesRepeat = np.random.randint(2, 6)
|
||||||
|
instructions.append("ori x" + reg1 + ", x" + reg1 + ", " + "1") # ensure reg1 is not 0
|
||||||
|
instructions.append("addi x" + reg2 + ", x" + reg1 + ", MASK_XLEN(" + str(numTimesRepeat) + ")") #r2 = r1 - numTimesRepeat (2 - 6)
|
||||||
|
instructions.append(str(self.prevLabel) + ":")
|
||||||
|
instructions.append("addi x" + reg2 + ", x" + reg2 + ", -1")
|
||||||
|
|
||||||
|
elif instr == "blt":
|
||||||
|
numTimesRepeat = np.random.randint(2, 6)
|
||||||
|
instructions.append("addi x" + reg2 + ", x" + reg1 + ", MASK_XLEN(" + str(numTimesRepeat) + ")") #r2 = r1 - numTimesRepeat (2 - 6)
|
||||||
|
instructions.append(str(self.prevLabel) + ":")
|
||||||
|
instructions.append("addi x" + reg2 + ", x" + reg2 + ", -1")
|
||||||
|
|
||||||
|
elif instr == "bgeu" or instr == "bge":
|
||||||
|
numTimesRepeat = np.random.randint(2, 6)*(-1)
|
||||||
|
instructions.append("addi x" + reg2 + ", x" + reg1 + ", MASK_XLEN(" + str(numTimesRepeat) + ")") #r2 = r1 + numTimesRepeat (2 - 6)
|
||||||
|
instructions.append(str(self.prevLabel) + ":")
|
||||||
|
instructions.append("addi x" + reg2 + ", x" + reg2 + ", 1")
|
||||||
|
|
||||||
|
# Junk instructions
|
||||||
|
numInstr = np.random.randint(0, 5)
|
||||||
|
reg_check = 1
|
||||||
|
for i in range(0, numInstr):
|
||||||
|
curr = self.getRandInstruction(self.instrDict.INSTR_DEST_SRC1_SRC2)
|
||||||
|
rd = self.randSelect.randReg(self.anyReg)
|
||||||
|
reg_check = rd
|
||||||
|
while rd == reg1 or rd==reg2:
|
||||||
|
rd = self.randSelect.randReg(self.anyReg)
|
||||||
|
r1 = self.randSelect.randReg(self.anyReg)
|
||||||
|
r2 = self.randSelect.randReg(self.anyReg)
|
||||||
|
instructions.append(curr + " x" + rd + ", x" + r1 + ", x" + r2)
|
||||||
|
|
||||||
|
check_instr = self.genTestInstr(reg_check)
|
||||||
|
for check in check_instr:
|
||||||
|
instructions.append(check)
|
||||||
|
instructions.append(instr + " x" + reg1 + ", x" + reg2 + ", " + str(self.prevLabel) + "b")
|
||||||
|
self.prevLabel += 1
|
||||||
|
|
||||||
|
return instructions
|
||||||
|
|
||||||
|
# have (1-5) sudo random alu instructions for backwards branch, (0-5) for forward
|
||||||
|
|
||||||
|
# randomly determine if branch is taken or not
|
||||||
|
# if branch not taken,
|
||||||
|
# we go by specific instruction and do some bit swizzling to make it false
|
||||||
|
|
||||||
|
# if branch taken
|
||||||
|
# add specific instruction to make branch true
|
||||||
|
# for backwards, have alu instructions change comparison flags to be true
|
||||||
|
|
||||||
|
def genTestInstr(self, reg):
|
||||||
|
out = ["sw x" + str(reg) + ", "+ str(self.test_count) + "(x6)"]
|
||||||
|
out.append("RVTEST_IO_ASSERT_GPR_EQ(x7, x{}, 0xdeadbeef) ".format(reg))
|
||||||
|
self.test_count += 4
|
||||||
|
|
||||||
|
if (self.test_count == 2044):
|
||||||
|
# Reset
|
||||||
|
wreset = "addi x6, x6, MASK_XLEN(2044)"
|
||||||
|
self.test_count = 0
|
||||||
|
out.append(wreset)
|
||||||
|
|
||||||
|
return out
|
||||||
|
|
||||||
|
def genInstruction(self):
|
||||||
|
num = np.random.randint(0, 20)
|
||||||
|
instr = ""
|
||||||
|
if (self.xlen == 64) and (num == 20):
|
||||||
|
instr = self.getRandInstruction(self.InstrDict.INSTR_RV64M)
|
||||||
|
else:
|
||||||
|
instr = self.getRandInstruction(self.InstrDict.INSTR_RV32I)
|
||||||
|
|
||||||
|
num = np.random.randint(0, 2) # 0 mem reg, on 1 do forwarding stuff
|
||||||
|
if instr in self.InstrDict.INSTR_MEM and num == 1:
|
||||||
|
return self.getForwardingInstructions(instr)
|
||||||
|
|
||||||
|
if instr in self.InstrDict.INSTR_SRC1_SRC2_LABEL:
|
||||||
|
return self.branchInstruction(instr)
|
||||||
|
|
||||||
|
if instr in self.InstrDict.INSTR_DEST_LABEL:
|
||||||
|
return self.jumpInstruction(instr)
|
||||||
|
|
||||||
|
fields, alignment = self.instrDict.instr[instr]
|
||||||
|
output = ""
|
||||||
|
rd = 1
|
||||||
|
for field in fields:
|
||||||
|
if field == NAME:
|
||||||
|
output += instr + " "
|
||||||
|
|
||||||
|
elif field == REG:
|
||||||
|
rd = self.randSelect.randReg(self.anyReg)
|
||||||
|
output += "x" + str(rd) + ", "
|
||||||
|
|
||||||
|
elif field == IMM and instr != "lui" and instr != "auipc":
|
||||||
|
output += "SEXT_IMM(" + self.randSelect.randHex(False, 3, alignment) + ")"
|
||||||
|
|
||||||
|
elif field == IMM and (instr == "lui" or instr == "auipc"):
|
||||||
|
output += self.randSelect.randHex(False, 3, alignment)
|
||||||
|
|
||||||
|
elif field == ADDR:
|
||||||
|
output += self.memoryAdrList[np.random.randint(0, len(self.memoryAdrList))]
|
||||||
|
output += "("
|
||||||
|
output += "x" + self.randSelect.randReg(self.memReg)
|
||||||
|
output += ")"
|
||||||
|
|
||||||
|
elif field == ZIMM:
|
||||||
|
if (instr in self.instrDict.INSTR_DEST_SRC1_ZIMM):
|
||||||
|
output += "SEXT_IMM(" + str(hex(np.random.randint(0, 32))) + ")" # has to be between 0 and 31
|
||||||
|
else:
|
||||||
|
output += "SEXT_IMM(" + self.randSelect.randHex(True, 3, alignment) + ")"
|
||||||
|
|
||||||
|
elif field == LABEL:
|
||||||
|
output += str(self.prevLabel)
|
||||||
|
|
||||||
|
if output[-2:] == ", ":
|
||||||
|
output = output[0:-2]
|
||||||
|
|
||||||
|
out_instr = [output]
|
||||||
|
check_instr = self.genTestInstr(rd)
|
||||||
|
for check in check_instr:
|
||||||
|
out_instr.append(check)
|
||||||
|
return out_instr
|
||||||
|
|
||||||
|
def setRegisters(self):
|
||||||
|
out = []
|
||||||
|
for reg in self.anyReg:
|
||||||
|
out.append('li x{}, MASK_XLEN({})'.format(reg, self.randSelect.randHex(False, 5, 1)))
|
||||||
|
return out
|
||||||
|
|
||||||
|
def populateMemory(self):
|
||||||
|
for i in range(0, 5):
|
||||||
|
val = self.randSelect.randDec(-1000, 1000, WORD)
|
||||||
|
while val in self.memoryAdrList:
|
||||||
|
val = self.randSelect.randDec(-1000, 1000, WORD)
|
||||||
|
self.memoryAdrList.append(str(val))
|
||||||
|
|
||||||
|
def generateInstructions(self, numInstructions):
|
||||||
|
instructions = []
|
||||||
|
for i in range(0, numInstructions):
|
||||||
|
instr = self.genInstruction()
|
||||||
|
for j in instr:
|
||||||
|
instructions.append(j)
|
||||||
|
return instructions
|
||||||
|
|
||||||
|
class RandInstrGenerator(InstrGenerator):
|
||||||
|
pass
|
||||||
|
|
||||||
|
class HazardInstrGenerator(InstrGenerator):
|
||||||
|
pass
|
||||||
|
|
||||||
|
# xlens = [32, 64]
|
||||||
|
xlens = [64]
|
||||||
|
for xlen in xlens:
|
||||||
|
|
||||||
|
test = "PIPELINE"
|
||||||
|
np.random.seed(42)
|
||||||
|
instrGen = InstrGenerator(10, xlen)
|
||||||
|
|
||||||
|
# write instructions to file
|
||||||
|
imperaspath = "../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "wally/"
|
||||||
|
basename = "WALLY-" + test
|
||||||
|
fname = imperaspath + "src/" + basename + ".S"
|
||||||
|
refname = imperaspath + "references/" + basename + ".reference_output"
|
||||||
|
|
||||||
|
|
||||||
|
# FOR LOCAL TESTING
|
||||||
|
# fname = "PIPELINE_TEST.S"
|
||||||
|
|
||||||
|
# print custom header part
|
||||||
|
f = open(fname, "w")
|
||||||
|
r = open(refname, "w")
|
||||||
|
line = "///////////////////////////////////////////\n"
|
||||||
|
f.write(line)
|
||||||
|
lines="// "+fname+ "\n// " + "Ethan Falicov & Shriya Nadgauda" + "\n"
|
||||||
|
f.write(lines)
|
||||||
|
line ="// Created " + str(datetime.now()) + "\n" + "\n"
|
||||||
|
f.write(line)
|
||||||
|
line = "// Begin Tests" + "\n"
|
||||||
|
f.write(line)
|
||||||
|
|
||||||
|
|
||||||
|
# insert generic header
|
||||||
|
h = open("testgen_header.S", "r")
|
||||||
|
for line in h:
|
||||||
|
f.write(line)
|
||||||
|
f.write("\n")
|
||||||
|
|
||||||
|
|
||||||
|
#set registerss
|
||||||
|
reg_instr = instrGen.setRegisters()
|
||||||
|
for instr in reg_instr:
|
||||||
|
f.write("\t" + instr + "\n")
|
||||||
|
|
||||||
|
# write instructions
|
||||||
|
testnum = 500
|
||||||
|
instructions = instrGen.generateInstructions(testnum)
|
||||||
|
for instr in instructions:
|
||||||
|
f.write("\t" + instr + "\n")
|
||||||
|
if ("RVTEST_IO_ASSERT_GPR_EQ" in instr):
|
||||||
|
f.write("\n")
|
||||||
|
|
||||||
|
|
||||||
|
# print footer
|
||||||
|
h = open("testgen_footer.S", "r")
|
||||||
|
for line in h:
|
||||||
|
f.write(line)
|
||||||
|
|
||||||
|
# Finish
|
||||||
|
lines = ".fill " + str(testnum) + ", " + str(xlen//8) + ", -1\n"
|
||||||
|
lines = lines + "\nRV_COMPLIANCE_DATA_END\n"
|
||||||
|
f.write(lines)
|
||||||
|
f.close()
|
||||||
|
r.close()
|
||||||
|
|
||||||
|
print("Done with ", xlen)
|
||||||
Loading…
Reference in New Issue
Block a user