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Add power analysis to synth.tcl

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This commit is contained in:
James E. Stine 2022-02-09 16:04:20 -06:00
parent ed4e912413
commit 216e050ecf
1 changed files with 19 additions and 10 deletions
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15
synthDC/scripts/synth.tcl
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@ -1,7 +1,11 @@
#
# OKSTATE Main Synopsys Flow
# Updated Sep 27, 2015 jes
# Synthesis Synopsys Flow
# james.stine@okstate.edu 27 Sep 2015
#
# Enables name mapping
saif_map -start
# get outputDir from environment (Makefile)
set outputDir $::env(OUTPUTDIR)
set cfgName $::env(CONFIG)
@ -15,7 +19,6 @@ eval file copy -force [glob ${hdl_src}/../config/shared/*.vh] {hdl/}
eval file copy -force [glob ${hdl_src}/*/*.sv] {hdl/}
eval file copy -force [glob ${hdl_src}/*/flop/*.sv] {hdl/}
# Verilog files
set my_verilog_files [glob hdl/*]
@ -48,6 +51,12 @@ link
# Reset all constraints
reset_design
# SAIF power prediction (optional)
# set_power_prediction
# Power Dissipation Analysis
# read_saif -input vcd/mult.saif -instance_name stimulus/dut -auto_map_names -verbose
# Set reset false path
set_false_path -from [get_ports reset]