From 20a04d8cee5c137c855646e3cad8bd23421bdc94 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 8 Aug 2021 11:42:10 -0500 Subject: [PATCH] Fixed another bug with AMO. If the CPU stalled as an AMO was finishing, the write to the cache's SRAM would occur. Then in the next cycle the SRAM would be reread while stalled providing the new update dated rather than the correct older value. --- wally-pipelined/regression/linux-wave.do | 122 +++++++++--------- wally-pipelined/regression/wally-buildroot.do | 2 +- wally-pipelined/src/cache/dcache.sv | 25 +++- 3 files changed, 82 insertions(+), 67 deletions(-) diff --git a/wally-pipelined/regression/linux-wave.do b/wally-pipelined/regression/linux-wave.do index 386a8bf80..5e1acc73b 100644 --- a/wally-pipelined/regression/linux-wave.do +++ b/wally-pipelined/regression/linux-wave.do @@ -12,43 +12,42 @@ add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/MemAdrM add wave -noupdate -expand -group {WriteBack stage} /testbench/dut/hart/ieu/InstrValidW -add wave -noupdate /testbench/dut/hart/ieu/dp/ResultM -add wave -noupdate /testbench/dut/hart/ieu/dp/ResultW -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM -add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM -add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM -add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/RetM -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/TrapM -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/StoreStallD -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/ICacheStallF -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/LSUStall -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/MulDivStallD -add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF -add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushD -add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushE -add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushM -add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushW -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW +add wave -noupdate -expand -group {WriteBack stage} /testbench/PCW +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM +add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM +add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM +add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM +add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE +add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM +add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/RetM +add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/TrapM +add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD +add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/StoreStallD +add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/ICacheStallF +add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/LSUStall +add wave -noupdate -group HDU -group hazards /testbench/dut/hart/MulDivStallD +add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF +add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD +add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE +add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM +add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]} @@ -365,13 +364,13 @@ add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /test add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerInstrPageFaultF add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerLoadPageFaultM add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerStorePageFaultM -add wave -noupdate -group csr /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW -add wave -noupdate -group csr /testbench/dut/hart/priv/csr/MIP_REGW -add wave -noupdate -group csr /testbench/dut/hart/priv/csr/genblk1/csrm/MSTATUS_REGW -add wave -noupdate -group csr /testbench/dut/hart/priv/csr/genblk1/csrm/MEPC_REGW -add wave -noupdate -group csr /testbench/dut/hart/priv/csr/genblk1/csrm/MTVAL_REGW -add wave -noupdate -group csr /testbench/dut/hart/priv/csr/STVEC_REGW -add wave -noupdate -group csr /testbench/dut/hart/priv/csr/MTVEC_REGW +add wave -noupdate -expand -group csr /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW +add wave -noupdate -expand -group csr /testbench/dut/hart/priv/csr/MIP_REGW +add wave -noupdate -expand -group csr /testbench/dut/hart/priv/csr/genblk1/csrm/MSTATUS_REGW +add wave -noupdate -expand -group csr /testbench/dut/hart/priv/csr/genblk1/csrm/MEPC_REGW +add wave -noupdate -expand -group csr /testbench/dut/hart/priv/csr/genblk1/csrm/MTVAL_REGW +add wave -noupdate -expand -group csr /testbench/dut/hart/priv/csr/STVEC_REGW +add wave -noupdate -expand -group csr /testbench/dut/hart/priv/csr/MTVEC_REGW add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/TLBWrite add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress @@ -445,29 +444,30 @@ add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HSELUART add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HADDR add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWRITE add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWDATA -add wave -noupdate -group {debug trace} -expand -group wb /testbench/dut/hart/ieu/c/InstrValidW -add wave -noupdate -group {debug trace} -expand -group wb /testbench/checkInstrW -add wave -noupdate -group {debug trace} -expand -group wb /testbench/PCW -add wave -noupdate -group {debug trace} -expand -group wb /testbench/ExpectedPCW -add wave -noupdate -group {debug trace} /testbench/line -add wave -noupdate -group {debug trace} /testbench/textM -add wave -noupdate -group {debug trace} /testbench/textW -add wave -noupdate -group {debug trace} /testbench/TrapW -add wave -noupdate -group {debug trace} -color Brown /testbench/dut/hart/hzu/TrapM -add wave -noupdate -group {debug trace} -expand -group mem -color Yellow /testbench/dut/hart/FlushW -add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/hart/priv/trap/InstrValidM -add wave -noupdate -group {debug trace} -expand -group mem /testbench/checkInstrM -add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/hart/PCM -add wave -noupdate -group {debug trace} -expand -group mem /testbench/ExpectedPCM +add wave -noupdate -expand -group {debug trace} -expand -group wb /testbench/dut/hart/ieu/c/InstrValidW +add wave -noupdate -expand -group {debug trace} -expand -group wb /testbench/checkInstrW +add wave -noupdate -expand -group {debug trace} -expand -group wb /testbench/PCW +add wave -noupdate -expand -group {debug trace} -expand -group wb /testbench/ExpectedPCW +add wave -noupdate -expand -group {debug trace} /testbench/line +add wave -noupdate -expand -group {debug trace} /testbench/textM +add wave -noupdate -expand -group {debug trace} /testbench/textW +add wave -noupdate -expand -group {debug trace} /testbench/TrapW +add wave -noupdate -expand -group {debug trace} -color Brown /testbench/dut/hart/hzu/TrapM +add wave -noupdate -expand -group {debug trace} -expand -group mem -color Yellow /testbench/dut/hart/FlushW +add wave -noupdate -expand -group {debug trace} -expand -group mem /testbench/dut/hart/priv/trap/InstrValidM +add wave -noupdate -expand -group {debug trace} -expand -group mem /testbench/checkInstrM +add wave -noupdate -expand -group {debug trace} -expand -group mem /testbench/dut/hart/PCM +add wave -noupdate -expand -group {debug trace} -expand -group mem /testbench/ExpectedPCM add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PCNext2F add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PrivilegedNextPCM add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PrivilegedChangePCM add wave -noupdate -group {pc selection} /testbench/dut/hart/priv/PrivilegedNextPCM add wave -noupdate -group {pc selection} /testbench/dut/hart/priv/trap/PrivilegedVectoredTrapVector add wave -noupdate -group {pc selection} /testbench/dut/hart/priv/trap/PrivilegedTrapVector +add wave -noupdate -radix unsigned /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/INSTRET_REGW TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 6} {41720414 ns} 0} {{Cursor 6} {41705401 ns} 0} {{Cursor 7} {41639056 ns} 0} -quietly wave cursor active 3 +WaveRestoreCursors {{Cursor 6} {165345795 ns} 0} {{Cursor 6} {41705547 ns} 0} {{Cursor 7} {41639055 ns} 0} +quietly wave cursor active 1 configure wave -namecolwidth 250 configure wave -valuecolwidth 297 configure wave -justifyvalue left @@ -482,4 +482,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {41638967 ns} {41639135 ns} +WaveRestoreZoom {165345739 ns} {165345955 ns} diff --git a/wally-pipelined/regression/wally-buildroot.do b/wally-pipelined/regression/wally-buildroot.do index cd0157800..43428e289 100644 --- a/wally-pipelined/regression/wally-buildroot.do +++ b/wally-pipelined/regression/wally-buildroot.do @@ -37,7 +37,7 @@ vsim workopt -suppress 8852,12070 add log -r /* do linux-wave.do -run 100 ms +run 300 ms #-- Run the Simulation #run -all diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index ad6f01a7e..1109f1d1c 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -208,7 +208,8 @@ module dcache STATE_PTW_FAULT_UNCACHED_READ, STATE_PTW_FAULT_UNCACHED_READ_DONE, - STATE_CPU_BUSY} statetype; + STATE_CPU_BUSY, + STATE_CPU_BUSY_FINISH_AMO} statetype; statetype CurrState, NextState; @@ -497,15 +498,15 @@ module dcache else if(AtomicM[1] & (&MemRWM) & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin SelAdrM = 2'b01; DCacheStall = 1'b0; - SRAMWordWriteEnableM = 1'b1; - SetDirtyM = 1'b1; - LRUWriteEn = 1'b1; if(StallWtoDCache) begin - NextState = STATE_CPU_BUSY; + NextState = STATE_CPU_BUSY_FINISH_AMO; SelAdrM = 2'b01; end else begin + SRAMWordWriteEnableM = 1'b1; + SetDirtyM = 1'b1; + LRUWriteEn = 1'b1; NextState = STATE_READY; end end @@ -805,6 +806,20 @@ module dcache end end + STATE_CPU_BUSY_FINISH_AMO: begin + CommittedM = 1'b1; + if(StallWtoDCache) begin + NextState = STATE_CPU_BUSY; + SelAdrM = 2'b01; + end + else begin + SRAMWordWriteEnableM = 1'b1; + SetDirtyM = 1'b1; + LRUWriteEn = 1'b1; + NextState = STATE_READY; + end + end + STATE_UNCACHED_WRITE : begin DCacheStall = 1'b1; AHBWrite = 1'b1;