From 1f7d732dca3d56f1d4943cb324d49259ef40903c Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Fri, 24 May 2024 16:10:58 -0500 Subject: [PATCH] Moved the rvvisynth code to testbench since I only want this for simulation and fpga. --- sim/questa/wave.do | 38 ++++++------- src/rvvi/rvvisynth.sv | 100 ++++++++++++++++----------------- src/wally/wallypipelinedsoc.sv | 88 +---------------------------- testbench/testbench.sv | 92 +++++++++++++++++++++++++++++- testbench/wallywrapper.sv | 5 +- 5 files changed, 166 insertions(+), 157 deletions(-) diff --git a/sim/questa/wave.do b/sim/questa/wave.do index a1ae5fe8f..ec8dd82b3 100644 --- a/sim/questa/wave.do +++ b/sim/questa/wave.do @@ -660,25 +660,25 @@ add wave -noupdate -group wfi /testbench/dut/core/priv/priv/pmd/WFITimeoutM add wave -noupdate -expand -group testbench /testbench/DCacheFlushStart add wave -noupdate /testbench/dut/core/lsu/hptw/hptw/HPTWLoadPageFault add wave -noupdate /testbench/dut/core/lsu/hptw/hptw/HPTWLoadPageFaultDelay -add wave -noupdate /testbench/dut/rvvisynth/CSRs -add wave -noupdate -expand -group rvvi /testbench/dut/rvvisynth/clk -add wave -noupdate -expand -group rvvi /testbench/dut/rvvisynth/rvvi -add wave -noupdate -expand -group rvvi /testbench/dut/rvvisynth/valid -add wave -noupdate -expand -group packetizer -color Gold /testbench/dut/packetizer/CurrState -add wave -noupdate -expand -group packetizer -radix unsigned /testbench/dut/packetizer/WordCount -add wave -noupdate -expand -group packetizer /testbench/dut/packetizer/RVVIStall -add wave -noupdate -expand -group packetizer -expand -group axi-write-interface /testbench/dut/packetizer/m_axi_wdata -add wave -noupdate -expand -group packetizer -expand -group axi-write-interface /testbench/dut/packetizer/m_axi_wlast -add wave -noupdate -expand -group packetizer -expand -group axi-write-interface /testbench/dut/packetizer/m_axi_wstrb -add wave -noupdate -expand -group packetizer -expand -group axi-write-interface /testbench/dut/packetizer/m_axi_wvalid -add wave -noupdate -expand -group packetizer -expand -group axi-write-interface /testbench/dut/packetizer/m_axi_wready -add wave -noupdate -expand -group eth /testbench/dut/ethernet/mii_tx_clk -add wave -noupdate -expand -group eth /testbench/dut/ethernet/mii_txd -add wave -noupdate -expand -group eth /testbench/dut/ethernet/mii_tx_en -add wave -noupdate -expand -group eth /testbench/dut/ethernet/mii_tx_er +add wave -noupdate -expand -group rvvi /testbench/rvvi_synth/rvvisynth/clk +add wave -noupdate -expand -group rvvi /testbench/rvvi_synth/rvvisynth/rvvi +add wave -noupdate -expand -group rvvi /testbench/rvvi_synth/rvvisynth/valid +add wave -noupdate -group packetizer -color Gold /testbench/rvvi_synth/packetizer/CurrState +add wave -noupdate -group packetizer -radix unsigned /testbench/rvvi_synth/packetizer/WordCount +add wave -noupdate -group packetizer /testbench/rvvi_synth/packetizer/RVVIStall +add wave -noupdate -group packetizer /testbench/rvvi_synth/packetizer/rvviDelay +add wave -noupdate -group packetizer -expand -group axi-write-interface /testbench/rvvi_synth/packetizer/m_axi_wdata +add wave -noupdate -group packetizer -expand -group axi-write-interface /testbench/rvvi_synth/packetizer/m_axi_wlast +add wave -noupdate -group packetizer -expand -group axi-write-interface /testbench/rvvi_synth/packetizer/m_axi_wstrb +add wave -noupdate -group packetizer -expand -group axi-write-interface /testbench/rvvi_synth/packetizer/m_axi_wvalid +add wave -noupdate -group packetizer -expand -group axi-write-interface /testbench/rvvi_synth/packetizer/m_axi_wready +add wave -noupdate -expand -group eth /testbench/rvvi_synth/ethernet/mii_tx_clk +add wave -noupdate -expand -group eth /testbench/rvvi_synth/ethernet/mii_txd +add wave -noupdate -expand -group eth /testbench/rvvi_synth/ethernet/mii_tx_en +add wave -noupdate -expand -group eth /testbench/rvvi_synth/ethernet/mii_tx_er TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {650 ns} 1} {{Cursor 4} {2090 ns} 1} {{Cursor 3} {364 ns} 0} -quietly wave cursor active 3 +WaveRestoreCursors {{Cursor 4} {640 ns} 1} {{Cursor 4} {2400 ns} 1} {{Cursor 3} {554 ns} 0} {{Cursor 4} {120089 ns} 0} +quietly wave cursor active 4 configure wave -namecolwidth 250 configure wave -valuecolwidth 194 configure wave -justifyvalue left @@ -693,4 +693,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {266 ns} {618 ns} +WaveRestoreZoom {0 ns} {1033211 ns} diff --git a/src/rvvi/rvvisynth.sv b/src/rvvi/rvvisynth.sv index e5801cf09..27a1fe6d3 100644 --- a/src/rvvi/rvvisynth.sv +++ b/src/rvvi/rvvisynth.sv @@ -62,64 +62,64 @@ module rvvisynth import cvw::*; #(parameter cvw_t P, logic [MAX_CSRS*(P.XLEN+12)-1:0] CSRs; // get signals from the core. - assign StallE = core.StallE; - assign StallM = core.StallM; - assign StallW = core.StallW; - assign FlushE = core.FlushE; - assign FlushM = core.FlushM; - assign FlushW = core.FlushW; - assign InstrValidM = core.ieu.InstrValidM; - assign InstrRawD = core.ifu.InstrRawD; - assign PCM = core.ifu.PCM; - assign Mcycle = core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[0]; - assign Minstret = core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2]; - assign TrapM = core.TrapM; - assign PrivilegeModeW = core.priv.priv.privmode.PrivilegeModeW; - assign GPRAddr = core.ieu.dp.regf.a3; - assign GPRWen = core.ieu.dp.regf.we3; - assign GPRValue = core.ieu.dp.regf.wd3; - assign FPRAddr = core.fpu.fpu.fregfile.a4; - assign FPRWen = core.fpu.fpu.fregfile.we4; - assign FPRValue = core.fpu.fpu.fregfile.wd4; + assign StallE = dut.core.StallE; + assign StallM = dut.core.StallM; + assign StallW = dut.core.StallW; + assign FlushE = dut.core.FlushE; + assign FlushM = dut.core.FlushM; + assign FlushW = dut.core.FlushW; + assign InstrValidM = dut.core.ieu.InstrValidM; + assign InstrRawD = dut.core.ifu.InstrRawD; + assign PCM = dut.core.ifu.PCM; + assign Mcycle = dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[0]; + assign Minstret = dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2]; + assign TrapM = dut.core.TrapM; + assign PrivilegeModeW = dut.core.priv.priv.privmode.PrivilegeModeW; + assign GPRAddr = dut.core.ieu.dp.regf.a3; + assign GPRWen = dut.core.ieu.dp.regf.we3; + assign GPRValue = dut.core.ieu.dp.regf.wd3; + assign FPRAddr = dut.core.fpu.fpu.fregfile.a4; + assign FPRWen = dut.core.fpu.fpu.fregfile.we4; + assign FPRValue = dut.core.fpu.fpu.fregfile.wd4; - assign CSRArray[0] = core.priv.priv.csr.csrm.MSTATUS_REGW; // 12'h300 - assign CSRArray[1] = core.priv.priv.csr.csrm.MSTATUSH_REGW; // 12'h310 - assign CSRArray[2] = core.priv.priv.csr.csrm.MTVEC_REGW; // 12'h305 - assign CSRArray[3] = core.priv.priv.csr.csrm.MEPC_REGW; // 12'h341 - assign CSRArray[4] = core.priv.priv.csr.csrm.MCOUNTEREN_REGW; // 12'h306 - assign CSRArray[5] = core.priv.priv.csr.csrm.MCOUNTINHIBIT_REGW; // 12'h320 - assign CSRArray[6] = core.priv.priv.csr.csrm.MEDELEG_REGW; // 12'h302 - assign CSRArray[7] = core.priv.priv.csr.csrm.MIDELEG_REGW; // 12'h303 - assign CSRArray[8] = core.priv.priv.csr.csrm.MIP_REGW; // 12'h344 - assign CSRArray[9] = core.priv.priv.csr.csrm.MIE_REGW; // 12'h304 - assign CSRArray[10] = core.priv.priv.csr.csrm.MISA_REGW; // 12'h301 - assign CSRArray[11] = core.priv.priv.csr.csrm.MENVCFG_REGW; // 12'h30A - assign CSRArray[12] = core.priv.priv.csr.csrm.MHARTID_REGW; // 12'hF14 - assign CSRArray[13] = core.priv.priv.csr.csrm.MSCRATCH_REGW; // 12'h340 - assign CSRArray[14] = core.priv.priv.csr.csrm.MCAUSE_REGW; // 12'h342 - assign CSRArray[15] = core.priv.priv.csr.csrm.MTVAL_REGW; // 12'h343 + assign CSRArray[0] = dut.core.priv.priv.csr.csrm.MSTATUS_REGW; // 12'h300 + assign CSRArray[1] = dut.core.priv.priv.csr.csrm.MSTATUSH_REGW; // 12'h310 + assign CSRArray[2] = dut.core.priv.priv.csr.csrm.MTVEC_REGW; // 12'h305 + assign CSRArray[3] = dut.core.priv.priv.csr.csrm.MEPC_REGW; // 12'h341 + assign CSRArray[4] = dut.core.priv.priv.csr.csrm.MCOUNTEREN_REGW; // 12'h306 + assign CSRArray[5] = dut.core.priv.priv.csr.csrm.MCOUNTINHIBIT_REGW; // 12'h320 + assign CSRArray[6] = dut.core.priv.priv.csr.csrm.MEDELEG_REGW; // 12'h302 + assign CSRArray[7] = dut.core.priv.priv.csr.csrm.MIDELEG_REGW; // 12'h303 + assign CSRArray[8] = dut.core.priv.priv.csr.csrm.MIP_REGW; // 12'h344 + assign CSRArray[9] = dut.core.priv.priv.csr.csrm.MIE_REGW; // 12'h304 + assign CSRArray[10] = dut.core.priv.priv.csr.csrm.MISA_REGW; // 12'h301 + assign CSRArray[11] = dut.core.priv.priv.csr.csrm.MENVCFG_REGW; // 12'h30A + assign CSRArray[12] = dut.core.priv.priv.csr.csrm.MHARTID_REGW; // 12'hF14 + assign CSRArray[13] = dut.core.priv.priv.csr.csrm.MSCRATCH_REGW; // 12'h340 + assign CSRArray[14] = dut.core.priv.priv.csr.csrm.MCAUSE_REGW; // 12'h342 + assign CSRArray[15] = dut.core.priv.priv.csr.csrm.MTVAL_REGW; // 12'h343 assign CSRArray[16] = 0; // 12'hF11 assign CSRArray[17] = 0; // 12'hF12 assign CSRArray[18] = {{P.XLEN-12{1'b0}}, 12'h100}; //P.XLEN'h100; // 12'hF13 assign CSRArray[19] = 0; // 12'hF15 assign CSRArray[20] = 0; // 12'h34A // supervisor CSRs - assign CSRArray[21] = core.priv.priv.csr.csrs.csrs.SSTATUS_REGW; // 12'h100 - assign CSRArray[22] = core.priv.priv.csr.csrm.MIE_REGW & 12'h222; // 12'h104 - assign CSRArray[23] = core.priv.priv.csr.csrs.csrs.STVEC_REGW; // 12'h105 - assign CSRArray[24] = core.priv.priv.csr.csrs.csrs.SEPC_REGW; // 12'h141 - assign CSRArray[25] = core.priv.priv.csr.csrs.csrs.SCOUNTEREN_REGW; // 12'h106 - assign CSRArray[26] = core.priv.priv.csr.csrs.csrs.SENVCFG_REGW; // 12'h10A - assign CSRArray[27] = core.priv.priv.csr.csrs.csrs.SATP_REGW; // 12'h180 - assign CSRArray[28] = core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW; // 12'h140 - assign CSRArray[29] = core.priv.priv.csr.csrs.csrs.STVAL_REGW; // 12'h143 - assign CSRArray[30] = core.priv.priv.csr.csrs.csrs.SCAUSE_REGW; // 12'h142 - assign CSRArray[31] = core.priv.priv.csr.csrm.MIP_REGW & 12'h222 & core.priv.priv.csr.csrm.MIDELEG_REGW; // 12'h144 - assign CSRArray[32] = core.priv.priv.csr.csrs.csrs.STIMECMP_REGW; // 12'h14D + assign CSRArray[21] = dut.core.priv.priv.csr.csrs.csrs.SSTATUS_REGW; // 12'h100 + assign CSRArray[22] = dut.core.priv.priv.csr.csrm.MIE_REGW & 12'h222; // 12'h104 + assign CSRArray[23] = dut.core.priv.priv.csr.csrs.csrs.STVEC_REGW; // 12'h105 + assign CSRArray[24] = dut.core.priv.priv.csr.csrs.csrs.SEPC_REGW; // 12'h141 + assign CSRArray[25] = dut.core.priv.priv.csr.csrs.csrs.SCOUNTEREN_REGW; // 12'h106 + assign CSRArray[26] = dut.core.priv.priv.csr.csrs.csrs.SENVCFG_REGW; // 12'h10A + assign CSRArray[27] = dut.core.priv.priv.csr.csrs.csrs.SATP_REGW; // 12'h180 + assign CSRArray[28] = dut.core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW; // 12'h140 + assign CSRArray[29] = dut.core.priv.priv.csr.csrs.csrs.STVAL_REGW; // 12'h143 + assign CSRArray[30] = dut.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW; // 12'h142 + assign CSRArray[31] = dut.core.priv.priv.csr.csrm.MIP_REGW & 12'h222 & dut.core.priv.priv.csr.csrm.MIDELEG_REGW; // 12'h144 + assign CSRArray[32] = dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW; // 12'h14D // user CSRs - assign CSRArray[33] = core.priv.priv.csr.csru.csru.FFLAGS_REGW; // 12'h001 - assign CSRArray[34] = core.priv.priv.csr.csru.csru.FRM_REGW; // 12'h002 - assign CSRArray[35] = {core.priv.priv.csr.csru.csru.FRM_REGW, core.priv.priv.csr.csru.csru.FFLAGS_REGW}; // 12'h003 + assign CSRArray[33] = dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW; // 12'h001 + assign CSRArray[34] = dut.core.priv.priv.csr.csru.csru.FRM_REGW; // 12'h002 + assign CSRArray[35] = {dut.core.priv.priv.csr.csru.csru.FRM_REGW, dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW}; // 12'h003 // assign XLENZeros = '0; diff --git a/src/wally/wallypipelinedsoc.sv b/src/wally/wallypipelinedsoc.sv index 75265ab29..236a653fb 100644 --- a/src/wally/wallypipelinedsoc.sv +++ b/src/wally/wallypipelinedsoc.sv @@ -32,10 +32,12 @@ module wallypipelinedsoc import cvw::*; #(parameter cvw_t P) ( input logic reset_ext, // external asynchronous reset pin output logic reset, // reset synchronized to clk to prevent races on release // AHB Interface - input logic [P.AHBW-1:0] HRDATAEXT, + input logic [P.AHBW-1:0] HRDATAEXT, input logic HREADYEXT, HRESPEXT, output logic HSELEXT, output logic HSELEXTSDC, + // fpga debug signals + input logic RVVIStall, // outputs to external memory, shared with uncore memory output logic HCLK, HRESETn, output logic [P.PA_BITS-1:0] HADDR, @@ -68,11 +70,6 @@ module wallypipelinedsoc import cvw::*; #(parameter cvw_t P) ( logic [63:0] MTIME_CLINT; // from CLINT to CSRs logic MExtInt,SExtInt; // from PLIC - localparam MAX_CSRS = 3; - logic valid; - logic RVVIStall; - logic [187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12)-1:0] rvvi; - // synchronize reset to SOC clock domain synchronizer resetsync(.clk, .d(reset_ext), .q(reset)); @@ -95,84 +92,5 @@ module wallypipelinedsoc import cvw::*; #(parameter cvw_t P) ( MTIME_CLINT, GPIOOUT, GPIOEN, UARTSout, SPIOut, SPICS} = '0; end - - - rvvisynth #(P, MAX_CSRS) rvvisynth(.clk, .reset, .valid, .rvvi); - - // a bunch of these signals would be needed for the xilinx ethernet IP - // but I switched to using https://github.com/alexforencich/verilog-ethernet - // so most arn't needed anymore. *** remove once I've confirmed this - // works in synthesis. - logic [3:0] m_axi_awid; - logic [12:0] m_axi_awaddr; - logic [7:0] m_axi_awlen; - logic [2:0] m_axi_awsize; - logic [1:0] m_axi_awburst; - logic [3:0] m_axi_awcache; - logic m_axi_awvalid; - logic m_axi_awready; - // axi 4 write data channel - logic [31:0] m_axi_wdata; - logic [3:0] m_axi_wstrb; - logic m_axi_wlast; - logic m_axi_wvalid; - logic m_axi_wready; - // axi 4 write response channel - logic [3:0] m_axi_bid; - logic [1:0] m_axi_bresp; - logic m_axi_bvalid; - logic m_axi_bready; - // axi 4 read address channel - logic [3:0] m_axi_arid; - logic [12:0] m_axi_araddr; - logic [7:0] m_axi_arlen; - logic [2:0] m_axi_arsize; - logic [1:0] m_axi_arburst; - logic [3:0] m_axi_arcache; - logic m_axi_arvalid; - logic m_axi_arready; - // axi 4 read data channel - logic [3:0] m_axi_rid; - logic [31:0] m_axi_rdata; - logic [1:0] m_axi_rresp; - logic m_axi_rlast; - logic m_axi_rvalid; - logic m_axi_rready; - - logic [3:0] mii_txd; - logic mii_tx_en, mii_tx_er; - - logic tx_error_underflow, tx_fifo_overflow, tx_fifo_bad_frame, tx_fifo_good_frame, rx_error_bad_frame; - logic rx_error_bad_fcs, rx_fifo_overflow, rx_fifo_bad_frame, rx_fifo_good_frame; - - packetizer #(P, MAX_CSRS) packetizer(.rvvi, .valid, .m_axi_aclk(clk), .m_axi_aresetn(~reset), .RVVIStall, - .m_axi_awid, .m_axi_awaddr, .m_axi_awlen, .m_axi_awsize, .m_axi_awburst, .m_axi_awcache, .m_axi_awvalid, - .m_axi_awready, .m_axi_wdata, .m_axi_wstrb, .m_axi_wlast, .m_axi_wvalid, .m_axi_wready, .m_axi_bid, - .m_axi_bresp, .m_axi_bvalid, .m_axi_bready, .m_axi_arid, .m_axi_araddr, .m_axi_arlen, .m_axi_arsize, - .m_axi_arburst, .m_axi_arcache, .m_axi_arvalid, .m_axi_arready, .m_axi_rid, .m_axi_rdata, .m_axi_rresp, - .m_axi_rlast, .m_axi_rvalid, .m_axi_rready); - - eth_mac_mii_fifo #("GENERIC", "BUFG", 32) ethernet(.rst(reset), .logic_clk(clk), .logic_rst(reset), - .tx_axis_tdata(m_axi_wdata), .tx_axis_tkeep(m_axi_wstrb), .tx_axis_tvalid(m_axi_wvalid), .tx_axis_tready(m_axi_wready), - .tx_axis_tlast(m_axi_wlast), .tx_axis_tuser('0), .rx_axis_tdata(), .rx_axis_tkeep(), .rx_axis_tvalid(), .rx_axis_tready(1'b1), - .rx_axis_tlast(), .rx_axis_tuser(), - - // *** update these - .mii_rx_clk(clk), // *** need to be the mii clock - .mii_rxd('0), - .mii_rx_dv('0), - .mii_rx_er('0), - .mii_tx_clk(clk), // *** needs to be the mii clock - .mii_txd, - .mii_tx_en, - .mii_tx_er, - - // status - .tx_error_underflow, .tx_fifo_overflow, .tx_fifo_bad_frame, .tx_fifo_good_frame, .rx_error_bad_frame, - .rx_error_bad_fcs, .rx_fifo_overflow, .rx_fifo_bad_frame, .rx_fifo_good_frame, - .cfg_ifg(8'd12), .cfg_tx_enable(1'b1), .cfg_rx_enable(1'b1) - ); - - assign m_axi_awready = '1; endmodule diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 71aaa8126..ed511da68 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -33,6 +33,8 @@ `include "idv/idv.svh" `endif +// *** bug replace with config? +`define RVVI_SYNTH_SUPPORTED 1 import cvw::*; @@ -110,6 +112,7 @@ module testbench; logic Validate; logic SelectTest; logic TestComplete; + logic RVVIStall; initial begin // look for arguments passed to simulation, or use defaults @@ -577,7 +580,7 @@ module testbench; assign SDCIntr = 1'b0; end - wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, .HSELEXTSDC, + wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .RVVIStall, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, .HSELEXTSDC, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN, .UARTSin, .UARTSout, .SDCIntr, .SPIIn, .SPIOut, .SPICS); @@ -587,6 +590,93 @@ module testbench; clk = 1'b1; # 5; clk = 1'b0; # 5; end + if(`RVVI_SYNTH_SUPPORTED) begin : rvvi_synth + localparam MAX_CSRS = 3; + logic valid; + logic [187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12)-1:0] rvvi; + + rvvisynth #(P, MAX_CSRS) rvvisynth(.clk, .reset, .valid, .rvvi); + + // a bunch of these signals would be needed for the xilinx ethernet IP + // but I switched to using https://github.com/alexforencich/verilog-ethernet + // so most arn't needed anymore. *** remove once I've confirmed this + // works in synthesis. + logic [3:0] m_axi_awid; + logic [12:0] m_axi_awaddr; + logic [7:0] m_axi_awlen; + logic [2:0] m_axi_awsize; + logic [1:0] m_axi_awburst; + logic [3:0] m_axi_awcache; + logic m_axi_awvalid; + logic m_axi_awready; + // axi 4 write data channel + logic [31:0] m_axi_wdata; + logic [3:0] m_axi_wstrb; + logic m_axi_wlast; + logic m_axi_wvalid; + logic m_axi_wready; + // axi 4 write response channel + logic [3:0] m_axi_bid; + logic [1:0] m_axi_bresp; + logic m_axi_bvalid; + logic m_axi_bready; + // axi 4 read address channel + logic [3:0] m_axi_arid; + logic [12:0] m_axi_araddr; + logic [7:0] m_axi_arlen; + logic [2:0] m_axi_arsize; + logic [1:0] m_axi_arburst; + logic [3:0] m_axi_arcache; + logic m_axi_arvalid; + logic m_axi_arready; + // axi 4 read data channel + logic [3:0] m_axi_rid; + logic [31:0] m_axi_rdata; + logic [1:0] m_axi_rresp; + logic m_axi_rlast; + logic m_axi_rvalid; + logic m_axi_rready; + + logic [3:0] mii_txd; + logic mii_tx_en, mii_tx_er; + + logic tx_error_underflow, tx_fifo_overflow, tx_fifo_bad_frame, tx_fifo_good_frame, rx_error_bad_frame; + logic rx_error_bad_fcs, rx_fifo_overflow, rx_fifo_bad_frame, rx_fifo_good_frame; + + packetizer #(P, MAX_CSRS) packetizer(.rvvi, .valid, .m_axi_aclk(clk), .m_axi_aresetn(~reset), .RVVIStall, + .m_axi_awid, .m_axi_awaddr, .m_axi_awlen, .m_axi_awsize, .m_axi_awburst, .m_axi_awcache, .m_axi_awvalid, + .m_axi_awready, .m_axi_wdata, .m_axi_wstrb, .m_axi_wlast, .m_axi_wvalid, .m_axi_wready, .m_axi_bid, + .m_axi_bresp, .m_axi_bvalid, .m_axi_bready, .m_axi_arid, .m_axi_araddr, .m_axi_arlen, .m_axi_arsize, + .m_axi_arburst, .m_axi_arcache, .m_axi_arvalid, .m_axi_arready, .m_axi_rid, .m_axi_rdata, .m_axi_rresp, + .m_axi_rlast, .m_axi_rvalid, .m_axi_rready); + + eth_mac_mii_fifo #("GENERIC", "BUFG", 32) ethernet(.rst(reset), .logic_clk(clk), .logic_rst(reset), + .tx_axis_tdata(m_axi_wdata), .tx_axis_tkeep(m_axi_wstrb), .tx_axis_tvalid(m_axi_wvalid), .tx_axis_tready(m_axi_wready), + .tx_axis_tlast(m_axi_wlast), .tx_axis_tuser('0), .rx_axis_tdata(), .rx_axis_tkeep(), .rx_axis_tvalid(), .rx_axis_tready(1'b1), + .rx_axis_tlast(), .rx_axis_tuser(), + + // *** update these + .mii_rx_clk(clk), // *** need to be the mii clock + .mii_rxd('0), + .mii_rx_dv('0), + .mii_rx_er('0), + .mii_tx_clk(clk), // *** needs to be the mii clock + .mii_txd, + .mii_tx_en, + .mii_tx_er, + + // status + .tx_error_underflow, .tx_fifo_overflow, .tx_fifo_bad_frame, .tx_fifo_good_frame, .rx_error_bad_frame, + .rx_error_bad_fcs, .rx_fifo_overflow, .rx_fifo_bad_frame, .rx_fifo_good_frame, + .cfg_ifg(8'd12), .cfg_tx_enable(1'b1), .cfg_rx_enable(1'b1) + ); + + assign m_axi_awready = '1; + end else begin + assign RVVIStall = '0; + end + + /* // Print key info each cycle for debugging always @(posedge clk) begin diff --git a/testbench/wallywrapper.sv b/testbench/wallywrapper.sv index 990ebfe74..234a11fdf 100644 --- a/testbench/wallywrapper.sv +++ b/testbench/wallywrapper.sv @@ -57,7 +57,7 @@ module wallywrapper; logic HREADY; logic HSELEXT; logic HSELEXTSDC; - + logic RVVIStall; // instantiate device to be tested assign GPIOIN = 0; @@ -67,8 +67,9 @@ module wallywrapper; assign HRESPEXT = 0; assign HRDATAEXT = 0; + assign RVVIStall = '0; - wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT, .HSELEXTSDC, + wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .RVVIStall, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT, .HSELEXTSDC, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN, .UARTSin, .UARTSout, .SPIIn, .SPIOut, .SPICS, .SDCIntr);