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https://github.com/openhwgroup/cvw
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Fixed reference to deleted atomic signal in cache
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parent
1d234c05c9
commit
1f57df7f8b
@ -196,8 +196,8 @@ module lsu import cvw::*; #(parameter cvw_t P) (
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assign PreLSURWM = MemRWM;
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assign PreLSURWM = MemRWM;
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assign IHAdrM = IEUAdrExtM;
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assign IHAdrM = IEUAdrExtM;
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assign LSUFunct3M = Funct3M;
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assign LSUFunct3M = Funct3M;
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assign LSUFunct7M = Funct7M;
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assign LSUFunct7M = Funct7M;
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assign LSUAtomicM = AtomicM;
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assign LSUAtomicM = AtomicM;
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assign IHWriteDataM = WriteDataM;
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assign IHWriteDataM = WriteDataM;
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assign LoadAccessFaultM = LSULoadAccessFaultM;
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assign LoadAccessFaultM = LSULoadAccessFaultM;
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assign StoreAmoAccessFaultM = LSUStoreAmoAccessFaultM;
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assign StoreAmoAccessFaultM = LSUStoreAmoAccessFaultM;
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@ -182,7 +182,7 @@ module loggers import cvw::*; #(parameter cvw_t P,
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(!dut.core.lsu.bus.dcache.dcache.vict.cacheLRU.AllValid) ? "M" :
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(!dut.core.lsu.bus.dcache.dcache.vict.cacheLRU.AllValid) ? "M" :
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dut.core.lsu.bus.dcache.dcache.LineDirty ? "D" : "E";
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dut.core.lsu.bus.dcache.dcache.LineDirty ? "D" : "E";
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AccessTypeString = dut.core.lsu.bus.dcache.FlushDCache ? "F" :
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AccessTypeString = dut.core.lsu.bus.dcache.FlushDCache ? "F" :
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dut.core.lsu.bus.dcache.CacheAtomicM[1] ? "A" :
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dut.core.lsu.LSUAtomicM[1] ? "A" :
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dut.core.lsu.bus.dcache.CacheRWM == 2'b10 ? "R" :
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dut.core.lsu.bus.dcache.CacheRWM == 2'b10 ? "R" :
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dut.core.lsu.bus.dcache.CacheRWM == 2'b01 ? "W" :
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dut.core.lsu.bus.dcache.CacheRWM == 2'b01 ? "W" :
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"NULL";
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"NULL";
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