From 1f3dfa20f6c828774e2194ef5847fd08f2fcbf37 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Tue, 20 Jul 2021 14:46:37 -0400
Subject: [PATCH] flag for optional boottim

---
 wally-pipelined/config/rv64ic/wally-config.vh  | 2 --
 wally-pipelined/src/uncore/uncore.sv           | 2 +-
 wally-pipelined/testbench/testbench-imperas.sv | 1 +
 3 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/wally-pipelined/config/rv64ic/wally-config.vh b/wally-pipelined/config/rv64ic/wally-config.vh
index 88d3fd037..fab0a4dff 100644
--- a/wally-pipelined/config/rv64ic/wally-config.vh
+++ b/wally-pipelined/config/rv64ic/wally-config.vh
@@ -78,8 +78,6 @@
 
 // *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
 `define BOOTTIM_SUPPORTED 1'b1
-//`define BOOTTIM_RANGE  56'h00003FFF
-//`define BOOTTIM_BASE   56'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
 `define BOOTTIM_BASE   56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
 `define BOOTTIM_RANGE  56'h00000FFF
 `define TIM_SUPPORTED 1'b1
diff --git a/wally-pipelined/src/uncore/uncore.sv b/wally-pipelined/src/uncore/uncore.sv
index e5f5fdd7d..47bce83b6 100644
--- a/wally-pipelined/src/uncore/uncore.sv
+++ b/wally-pipelined/src/uncore/uncore.sv
@@ -87,7 +87,7 @@ module uncore (
   generate
     // tightly integrated memory
     dtim #(.BASE(`TIM_BASE), .RANGE(`TIM_RANGE)) dtim (.*);
-    //if (`BOOTTIM_SUPPORTED) *** restore when naming is figured out
+    if (`BOOTTIM_SUPPORTED) 
       dtim #(.BASE(`BOOTTIM_BASE), .RANGE(`BOOTTIM_RANGE)) bootdtim(.HSELTim(HSELBootTim), .HREADTim(HREADBootTim), .HRESPTim(HRESPBootTim), .HREADYTim(HREADYBootTim), .*);
 
     // memory-mapped I/O peripherals
diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv
index 079ac6b1e..2e15839eb 100644
--- a/wally-pipelined/testbench/testbench-imperas.sv
+++ b/wally-pipelined/testbench/testbench-imperas.sv
@@ -753,6 +753,7 @@ module riscvassertions();
     assert (`ICACHE_NUMWAYS == 1 || `MEM_ICACHE == 0) else $error("Multiple Instruction Cache ways not yet implemented");
     assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES) else $error("ITLB_ENTRIES must be a power of 2");
     assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES) else $error("DTLB_ENTRIES must be a power of 2");
+    assert (`TIM_RANGE >= 56'h07FFFFFF) else $error("Some regression tests will fail if TIM_RANGE is less than 56'h07FFFFFF");
   end
 endmodule