From 1ebc7aa95aba507c89bb1a22399e0412fc121fb0 Mon Sep 17 00:00:00 2001
From: Rose Thompson <ross1728@gmail.com>
Date: Sun, 3 Dec 2023 16:43:55 -0600
Subject: [PATCH] Optimized align.

---
 src/lsu/align.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/lsu/align.sv b/src/lsu/align.sv
index c618bb605..d3ca5ecc5 100644
--- a/src/lsu/align.sv
+++ b/src/lsu/align.sv
@@ -146,7 +146,7 @@ module align import cvw::*;  #(parameter cvw_t P) (
 
   // shifter (4:1 mux for 32 bit, 8:1 mux for 64 bit)
   // 8 * is for shifting by bytes not bits
-  assign ShiftAmount = MisalignedM & ~SelHPTW ? {AccessByteOffsetM, 3'b0} : '0; // AND gate
+  assign ShiftAmount = SelHPTW ? '0 : {AccessByteOffsetM, 3'b0}; // AND gate
   assign ReadDataWordSpillShiftedM = ReadDataWordSpillAllM >> ShiftAmount;
   assign DCacheReadDataWordSpillM = ReadDataWordSpillShiftedM[P.LLEN-1:0];