From 1ea8f99625ca9d8dd5553a1d2839b8fbbf778ad0 Mon Sep 17 00:00:00 2001 From: Marcus Mellor Date: Thu, 29 Feb 2024 11:13:56 -0600 Subject: [PATCH] soc/fifo: Add copyright headers --- soc/fifo/fifo.sv | 29 +++++++++++++++++++++++++++++ soc/fifo/fifomem.sv | 28 +++++++++++++++++++++++++++- soc/fifo/rptr_empty.sv | 28 ++++++++++++++++++++++++++++ soc/fifo/sync_r2w.sv | 28 ++++++++++++++++++++++++++++ soc/fifo/sync_w2r.sv | 28 ++++++++++++++++++++++++++++ soc/fifo/wptr_full.sv | 28 ++++++++++++++++++++++++++++ 6 files changed, 168 insertions(+), 1 deletion(-) diff --git a/soc/fifo/fifo.sv b/soc/fifo/fifo.sv index b6f3fcdc3..a5102a471 100644 --- a/soc/fifo/fifo.sv +++ b/soc/fifo/fifo.sv @@ -1,3 +1,32 @@ +/////////////////////////////////////////// +// fifo.sv +// +// Written: Clifford E Cummings 16 June 2005 +// Modified: james.stine@okstate.edu 19 February 2024 +// +// Purpose: Asynchronous FIFO +// +// Documentation: +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + module fifo #(parameter DSIZE = 8, parameter ASIZE = 4) (rdata, wfull, rempty, wdata, diff --git a/soc/fifo/fifomem.sv b/soc/fifo/fifomem.sv index 3e3665c0d..1c7fdc045 100644 --- a/soc/fifo/fifomem.sv +++ b/soc/fifo/fifomem.sv @@ -1,5 +1,31 @@ +/////////////////////////////////////////// +// fifomem.sv +// +// Written: Clifford E. Cummings 16 June 2005 +// Modified: james.stine@okstate.edu 19 February 2024 +// +// Purpose: FIFO memory buffer +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// -// DATASIZE = Memory data word width +// DATASIZE = Memory data word width // ADDRSIZE = Number of mem address bits module fifomem #(parameter DATASIZE = 8, parameter ADDRSIZE = 4) diff --git a/soc/fifo/rptr_empty.sv b/soc/fifo/rptr_empty.sv index 68ec5cb6e..79bb0fc08 100644 --- a/soc/fifo/rptr_empty.sv +++ b/soc/fifo/rptr_empty.sv @@ -1,3 +1,31 @@ +/////////////////////////////////////////// +// rptr_empty.sv +// +// Written: Clifford E Cummings 16 June 2005 +// Modified: james.stine@okstate.edu 19 February 2024 +// +// Purpose: FIFO read pointer and empty generation logic +// +// Documentation: +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// module rptr_empty #(parameter ADDRSIZE = 4) (rempty, raddr, rptr, rq2_wptr, rinc, rclk, rrst_n); diff --git a/soc/fifo/sync_r2w.sv b/soc/fifo/sync_r2w.sv index 97ac299a7..935d04f5a 100644 --- a/soc/fifo/sync_r2w.sv +++ b/soc/fifo/sync_r2w.sv @@ -1,3 +1,31 @@ +/////////////////////////////////////////// +// sync_r2w.sv +// +// Written: Clifford E Cummings 16 June 2005 +// Modified: james.stine@okstate.edu 19 February 2024 +// +// Purpose: FIFO read-domain to write-domain synchronizer +// +// Documentation: +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// module sync_r2w #(parameter ADDRSIZE = 4) (wq2_rptr, rptr, wclk, wrst_n); diff --git a/soc/fifo/sync_w2r.sv b/soc/fifo/sync_w2r.sv index f186968be..6a666bfc6 100644 --- a/soc/fifo/sync_w2r.sv +++ b/soc/fifo/sync_w2r.sv @@ -1,3 +1,31 @@ +/////////////////////////////////////////// +// sync_w2r.sv +// +// Written: Clifford E Cummings 16 June 2005 +// Modified: james.stine@okstate.edu 19 February 2024 +// +// Purpose: FIFO write-domain to read-domain synchronizer +// +// Documentation: +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// module sync_w2r #(parameter ADDRSIZE = 4) (rq2_wptr, wptr, rclk, rrst_n); diff --git a/soc/fifo/wptr_full.sv b/soc/fifo/wptr_full.sv index a6f4fdf9f..19ff6517e 100644 --- a/soc/fifo/wptr_full.sv +++ b/soc/fifo/wptr_full.sv @@ -1,3 +1,31 @@ +/////////////////////////////////////////// +// wptr_full.sv +// +// Written: Clifford E Cummings 16 June 2005 +// Modified: james.stine@okstate.edu 19 February 2024 +// +// Purpose: FIFO write pointer and full generation logic +// +// Documentation: +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// module wptr_full #(parameter ADDRSIZE = 4) (wfull, waddr, wptr, wq2_rptr, winc, wclk, wrst_n);