diff --git a/pipelined/srt/srt.sv b/pipelined/srt/srt.sv
index 044bac9c1..bc272b011 100644
--- a/pipelined/srt/srt.sv
+++ b/pipelined/srt/srt.sv
@@ -37,6 +37,8 @@ module srt #(parameter Nf=52) (
   input  logic Flush, // *** multiple pipe stages
   // Floating Point Inputs
   // later add exponents, signs, special cases
+  input  logic [10:0] SrcXExpE, SrcYExpE, // exponents, for double precision exponents are 11 bits
+  // end of floating point inputs
   input  logic [Nf-1:0] SrcXFrac, SrcYFrac,
   input  logic [`XLEN-1:0] SrcA, SrcB,
   input  logic [1:0] Fmt, // Floats: 00 = 16 bit, 01 = 32 bit, 10 = 64 bit, 11 = 128 bit
@@ -45,6 +47,7 @@ module srt #(parameter Nf=52) (
   input  logic       Int, // Choose integer inputss
   input  logic       Sqrt, // perform square root, not divide
   output logic [Nf-1:0] Quot, Rem, // *** later handle integers
+  output logic [10:0] Exp,  // output exponent is hardcoded for 11 bits for double precision
   output logic [3:0] Flags
 );
 
@@ -78,6 +81,9 @@ module srt #(parameter Nf=52) (
   // Partial Product Generation
   csa csa(WS, WC, Dsel, qp, WSA, WCA);
 
+  // Exponent division 
+  exp exp(SrcXExpE, SrcYExpE, Exp);
+
   srtpostproc postproc(rp, rm, Quot);
 endmodule
 
@@ -247,6 +253,14 @@ module csa #(parameter N=56) (
 		    (in2[54:0] & in3[54:0]), cin};
 endmodule
 
+//////////////
+// exponent //
+//////////////
+module exp(input [10:0] e1, e2,
+           output [10:0] e);       // for double precision, exponent is 11 bits
+  assign e = (e1 - e2) + 11'd1023; // bias is hardcoded
+endmodule
+
 //////////////
 // finaladd //
 //////////////