diff --git a/config/rv64gc/config.vh b/config/rv64gc/config.vh index a8b7f1b05..af6e4aebd 100644 --- a/config/rv64gc/config.vh +++ b/config/rv64gc/config.vh @@ -107,7 +107,7 @@ localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF; localparam BOOTROM_PRELOAD = 1'b0; localparam UNCORE_RAM_SUPPORTED = 1'b1; localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000; -localparam logic [63:0] UNCORE_RAM_RANGE = 64'h7FFFFFFF; +localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF; localparam UNCORE_RAM_PRELOAD = 1'b0; localparam EXT_MEM_SUPPORTED = 1'b0; localparam logic [63:0] EXT_MEM_BASE = 64'h80000000; diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-01.S index 548911c0c..d9ef62141 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-01.S @@ -87,8 +87,8 @@ test_cases: .8byte 0x0000000080016FF8, 0x00000000200804CF, write64_test# Vaddr 0xFFFFFFFFFFFFF000, Paddr 0x80201000 aligned kilopage # second page table to check context switches with satp -.8byte 0x8FFFF000, 0x200000CF, write64_test# Vaddr 0x0, Paddr 0x80000000 aligned gigapage -.8byte 0x8FFFF010, 0x200000CF, write64_test# Vaddr 0x8000_0000, Paddr 0x80000000: aligned gigapage (program and data memory so we can execute without jumping around) +.8byte 0x87FFF000, 0x200000CF, write64_test# Vaddr 0x0, Paddr 0x80000000 aligned gigapage +.8byte 0x87FFF010, 0x200000CF, write64_test# Vaddr 0x8000_0000, Paddr 0x80000000: aligned gigapage (program and data memory so we can execute without jumping around) # test 11.3.1.1.2 write values to Paddrs in each page # each of these values is used for 11.3.1.1.3 and some other tests, specified in the comments. @@ -192,7 +192,7 @@ test_cases: # test 11.3.1.4.1 SATP ASID and PPN fields (test having two page tables with different ASID) // *** .8byte 0xFFFFFFFFFFFFF888, 0x0220DEADBEEF0099, write64_test # write identical value to global PTE to make sure it's still in the TLB -.8byte 0x8FFFF, 0x11, goto_sv39 # go to SV39 on a second, very minimal page table +.8byte 0x87FFF, 0x11, goto_sv39 # go to SV39 on a second, very minimal page table .8byte 0x200AB0, 0x0000DEADBEEF0000, read64_test # Read success of old written value from a new page table mapping # test 11.3.1.4.2 Test Global mapping diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.S index 56d36aa6a..2fbdf48ca 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.S @@ -108,8 +108,8 @@ test_cases: .8byte 0x0000000080016FF8, 0x00000000200804CF, write64_test# Vaddr 0xFFFFFFFFFFFFF000, Paddr 0x80201000 aligned kilopage # second page table to check context switches with satp -.8byte 0x8FFFF000, 0x200000CF, write64_test# Vaddr 0x0, Paddr 0x80000000 aligned gigapage -.8byte 0x8FFFF010, 0x200000CF, write64_test# Vaddr 0x8000_0000, Paddr 0x80000000: aligned gigapage (program and data memory so we can execute without jumping around) +.8byte 0x87FFF000, 0x200000CF, write64_test# Vaddr 0x0, Paddr 0x80000000 aligned gigapage +.8byte 0x87FFF010, 0x200000CF, write64_test# Vaddr 0x8000_0000, Paddr 0x80000000: aligned gigapage (program and data memory so we can execute without jumping around) # test 11.3.1.1.2 write values to Paddrs in each page # each of these values is used for 11.3.1.1.3 and some other tests, specified in the comments. @@ -249,7 +249,7 @@ test_cases: # test 11.3.1.4.1 SATP ASID and PPN fields (test having two page tables with different ASID) // *** .8byte 0xFFFFFFFFFFFFF888, 0x0220DEADBEEF0099, write64_test # write identical value to global PTE to make sure it's still in the TLB -.8byte 0x8FFFF, 0x11, goto_sv39 # go to SV39 on a second, very minimal page table +.8byte 0x87FFF, 0x11, goto_sv39 # go to SV39 on a second, very minimal page table .8byte 0x200AB0, 0x0000DEADBEEF0000, read64_test # Read success of old written value from a new page table mapping # test 11.3.1.4.2 Test Global mapping diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-01.S index bb49f3e7a..b6161fb8b 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-01.S @@ -113,7 +113,7 @@ test_cases: .8byte 0x80200AC0, 0x0990DEADBEEF0033, write64_test # 11.3.1.3.2 .8byte 0x80200130, 0x0110DEADBEEF0077, write64_test # 11.3.1.3.2 .8byte 0x85212348, 0x0330DEADBEEF0440, write64_test # 11.3.1.3.3 -.8byte 0x88888000, 0x0000806711100393, write64_test # 11.3.1.3.5 write same executable code +.8byte 0x87888000, 0x0000806711100393, write64_test # 11.3.1.3.5 write same executable code .8byte 0x80203AA0, 0x0440DEADBEEF0BB0, write64_test # 11.3.1.3.7 # test 11.3.1.1.3 read values back from Paddrs without translation (this also verifies the previous test) @@ -187,7 +187,7 @@ test_cases: # test 11.3.1.3.5 eXecute flag # executes on pages with X = 1 already tested in 11.3.1.3.1 -.8byte 0x010088888000, 0x2, executable_test # execute fault when X=0 +.8byte 0x010087888000, 0x2, executable_test # execute fault when X=0 # In the following two tests, SVADU is not supported, so the software handles the A/D bits # Since SVADU is 0, Accesses to A/D=0 causes a fault for the trap handler to fix those bits diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-svadu-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-svadu-01.S index 5cecb41ce..dcea1ff33 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-svadu-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-svadu-01.S @@ -113,7 +113,7 @@ test_cases: .8byte 0x80200AC0, 0x0990DEADBEEF0033, write64_test # 11.3.1.3.2 .8byte 0x80200130, 0x0110DEADBEEF0077, write64_test # 11.3.1.3.2 .8byte 0x85212348, 0x0330DEADBEEF0440, write64_test # 11.3.1.3.3 -.8byte 0x88888000, 0x0000806711100393, write64_test # 11.3.1.3.5 write same executable code +.8byte 0x87888000, 0x0000806711100393, write64_test # 11.3.1.3.5 write same executable code .8byte 0x80203658, 0xDEADBEEFDEADBEEF, write64_test # 11.3.1.3.7(a) #.8byte 0x85bc0ab0, 0x0123456789abcdf0, write64_test # 11.3.1.1.4 @@ -188,7 +188,7 @@ test_cases: # test 11.3.1.3.5 eXecute flag # executes on pages with X = 1 already tested in 11.3.1.3.1 -.8byte 0x010088888000, 0x2, executable_test # execute fault when X=0 +.8byte 0x010087888000, 0x2, executable_test # execute fault when X=0 # In the following two tests, SVADU is supported, so the hardware handles the A/D bits