diff --git a/pipelined/config/shared/wally-shared.vh b/pipelined/config/shared/wally-shared.vh
index 0b1952edd..ca93d7e7b 100644
--- a/pipelined/config/shared/wally-shared.vh
+++ b/pipelined/config/shared/wally-shared.vh
@@ -123,7 +123,7 @@
 `define FPDUR ((`DIVN+2+(`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES)+(`RADIX/4))
 `define DURLEN ($clog2(`FPDUR+1))
 `define QLEN (`FPDUR*`LOGR*`DIVCOPIES)
-`define DIVb (`FPDUR*`LOGR*`DIVCOPIES)-1
+`define DIVb (`QLEN-1)
 
 
 `define USE_SRAM 0
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv
index cde357bfa..b992a0d83 100644
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv
@@ -79,5 +79,8 @@ module fdivsqrt(
     .X,.Dpreproc, .FirstWS(WS), .FirstWC(WC),
     .DivStartE, .Xe(XeE), .Ye(YeE), .XZeroE, .YZeroE,
     .DivBusy);
-  fdivsqrtpostproc fdivsqrtpostproc(.WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .Firstun, .SqrtM, .SpecialCaseM, .QmM, .WZero, .DivSM);
+  fdivsqrtpostproc fdivsqrtpostproc(
+    .WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .Firstun, 
+    .SqrtM, .SpecialCaseM, .remOp(Funct3E[1]),
+    .QmM, .WZero, .DivSM);
 endmodule
\ No newline at end of file
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
index e0acd0ed5..4600dfbd2 100644
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
@@ -31,13 +31,14 @@
 `include "wally-config.vh"
 
 module fdivsqrtpostproc(
-  input logic [`DIVb+3:0] WS, WC,
-  input logic [`DIVN-2:0]  D, // U0.N-1
-  input logic [`DIVb:0] FirstU, FirstUM, 
-  input logic [`DIVb+1:0] FirstC,
-  input logic  Firstun,
-  input logic SqrtM,
-  input logic SpecialCaseM,
+  input  logic [`DIVb+3:0] WS, WC,
+  input  logic [`DIVN-2:0]  D, // U0.N-1
+  input  logic [`DIVb:0] FirstU, FirstUM, 
+  input  logic [`DIVb+1:0] FirstC,
+  input  logic  Firstun,
+  input  logic SqrtM,
+  input  logic SpecialCaseM,
+  input  logic remOp,
   output logic [`DIVb:0] QmM, 
   output logic WZero,
   output logic DivSM
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
index e6fe1a793..f1882ad6f 100644
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
@@ -53,15 +53,15 @@ module fdivsqrtpreproc (
   logic  [$clog2(`NF+2)-1:0] XZeroCnt, YZeroCnt;
   logic  [`NE+1:0] Qe;
   // Intdiv signals
-  // logic  [`DIVN-1:0] ZeroBufX, ZeroBufY; add after Cedar Commit
+  logic  [`DIVN-1:0] ZeroBufX, ZeroBufY;
   logic  [`XLEN-1:0] PosA, PosB;
   logic  Signed, Aneg, Bneg;
 
   // ***can probably merge X LZC with conversion
   // cout the number of leading zeros
   // Muxes needed for Int; add after Cedar Commit
-  // assign ZeroBufX = Int ? {ForwardedSrcAE, {`DIVN-`XLEN{1'b0}}} : {Xm, {`DIVN-`NF{1'b0}}};
-  // assign ZeroBufY = Int ? {ForwardedSrcBE, {`DIVN-`XLEN{1'b0}}} : {Ym, {`DIVN-`NF{1'b0}}};
+  assign ZeroBufX = MDUE ? {ForwardedSrcAE, {`DIVN-`XLEN{1'b0}}} : {Xm, {`DIVN-`NF-1{1'b0}}};
+  assign ZeroBufY = MDUE ? {ForwardedSrcBE, {`DIVN-`XLEN{1'b0}}} : {Ym, {`DIVN-`NF-1{1'b0}}};
   lzc #(`NF+1) lzcX (Xm, XZeroCnt);
   lzc #(`NF+1) lzcY (Ym, YZeroCnt);
 
diff --git a/pipelined/src/fpu/postproc/divshiftcalc.sv b/pipelined/src/fpu/postproc/divshiftcalc.sv
index 8b6fc0936..58fd9b9b6 100644
--- a/pipelined/src/fpu/postproc/divshiftcalc.sv
+++ b/pipelined/src/fpu/postproc/divshiftcalc.sv
@@ -71,5 +71,5 @@ module divshiftcalc(
     assign DivDenormShiftAmt = DivDenormShiftPos ? DivDenormShift[`LOGNORMSHIFTSZ-1:0] : '0;
     assign DivShiftAmt = DivResDenorm ? DivDenormShiftAmt : NormShift;
 
-    assign DivShiftIn = {{`NF{1'b0}}, DivQm, {`NORMSHIFTSZ-`DIVb+1-`NF{1'b0}}};
+    assign DivShiftIn = {{`NF{1'b0}}, DivQm, {`NORMSHIFTSZ-`DIVb-1-`NF{1'b0}}};
 endmodule
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h
index 7146e8334..1293d23ad 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h
@@ -1073,9 +1073,16 @@ uart_data_wait:
     li a4, 0x61
 uart_read_LSR_IIR:
     lb t4, 0(t3) // save IIR before reading LSR mgith clear it
+//  check if t4 is the rxfifotime out interrupt if it is then read the fifo then go back and repeat this.
+    li t7, 6
+    beq t4, t7, uart_rxfifo_timout
     lb t5, 0(t2) // read LSR
     andi t6, t5, 0x61  // wait until all transmissions are done and data is ready
     bne a4, t6, uart_read_LSR_IIR
+uart_rxfifo_timout:
+//read the fifo until empty
+   j uart_read_LSR_IIR
+
 
 uart_data_ready:
     li t2, 0
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-timeout-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-timeout-01.S
index 3cf7a896e..1523b3699 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-timeout-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-timeout-01.S
@@ -85,3 +85,23 @@ END_TESTS
 
 TEST_STACK_AND_DATA
 
+        // in your isa
+        // first claim the plic's uart interrupt by reading the claim register corresponding to 10 on context 0.
+        // then you'll read all entires in the fifo. 
+        // then you'll write the completed plic register to 10 on context 0.
+        // claim and completed have the same address.
+        // then you'll return by mret.
+
+trap_handler:   
+        // this will only get uart interrupts
+        li s0, plicBaseAddr
+        addi s0, s0, 0x200004 // claim offset 
+        lw s1, 0(s0)
+
+        // check that s1 is 10 and not something else
+        // read uart rx fifo
+        
+
+        // completed
+        sw s1, 0(s0) // tells the plic the isr is done.
+        mret