Merge branch 'main' of https://github.com/openhwgroup/cvw into dev

benchmarks/embench/Makefile

@@ -44,7 +44,7 @@ sim: modelsim_build_memfile modelsim_run speed
 # launches modelsim to simulate tests on wally
 modelsim_run:
 	mkdir -p ../../sim/wkdir
-	(cd ../../sim/ && vsim -c -do "do wally-batch.do rv32gc embench")
+	(cd ../../sim/ && wsim rv32gc embench)
 	cd ../../benchmarks/embench/
 
 # builds the objdump based on the compiled c elf files

docs/docker/Dockerfile.regression

@@ -9,6 +9,7 @@ USER root
 
 COPY --chown=${USERNAME}:${USERNAME} . /home/${USERNAME}
 RUN chown -R ${USERNAME}:${USERNAME} /home/${USERNAME}
+RUN chown -R ${USERNAME}:${USERNAME} /home/${USERNAME}/cvw
 
 USER ${USERNAME}
 WORKDIR /home/${USERNAME}/cvw

docs/docker/Makefile

@@ -0,0 +1,18 @@
+QUESTA_HOME?=/cad/mentor/questa_sim-2023.4
+CVW_GIT?=""
+
+commanline:
+	podman run -it --rm \
+    -v cvw_temp:/home/cad/cvw \
+    -v $(QUESTA_HOME):/cad/mentor/questa_sim-xxxx.x_x \
+    --privileged --network=host \
+    wallysoc/regression_wally /bin/bash
+
+regression_openhw_cvw:
+	podman run \
+	-e CVW_GIT=$(CVW_GIT) \
+    -e CLEAN_CVW=1 -e BUILD_RISCOF=1 -e RUN_QUESTA=1 \
+    -v cvw_temp:/home/cad/cvw \
+    -v $(QUESTA_HOME):/cad/mentor/questa_sim-xxxx.x_x \
+    --privileged --network=host \
+    --rm wallysoc/regression_wally

docs/docker/README.md

@@ -21,7 +21,7 @@ If you have any other questions, please read the [troubleshooting]() first.
     - `xhost +localhost:${USER}` for host
 - [x] Regression Script
 - [x] Configure the license for Questa
-- [ ] Change the condition from empty string to 1
+- [x] Change the condition from empty string to 1
 - [x] Add linux testvector-generation
     - [x] Estimate the useless building intermediate files
 
@@ -98,7 +98,7 @@ podman volume create cvw_temp
 
 # run regression on the OpenHW/cvw
 podman run \
-    -e CLEAN_CVW= -e BUILD_RISCOF= -e RUN_QUESTA= \
+    -e CLEAN_CVW=1 -e BUILD_RISCOF=1 -e RUN_QUESTA=1 \
     -v cvw_temp:/home/cad/cvw \
     -v /cad/mentor/questa_sim-2023.4:/cad/mentor/questa_sim-xxxx.x_x \
     --privileged --network=host \
@@ -106,7 +106,7 @@ podman run \
 
 # run regression on the Karl-Han/cvw
 podman run \
-    -e CLEAN_CVW= -e BUILD_RISCOF= -e RUN_QUESTA= \
+    -e CLEAN_CVW=1 -e BUILD_RISCOF=1 -e RUN_QUESTA=1 \
     -e CVW_GIT=https://github.com/Karl-Han/cvw \
     -v cvw_temp:/home/cad/cvw \
     -v /cad/mentor/questa_sim-2023.4:/cad/mentor/questa_sim-xxxx.x_x \
@@ -115,7 +115,7 @@ podman run \
 
 # get into the container command line to debug or reading files
 podman run -it \
-    -e RUN_QUESTA= \
+    -e RUN_QUESTA=1 \
     -v cvw_temp:/home/cad/cvw \
     -v /cad/mentor/questa_sim-2023.4:/cad/mentor/questa_sim-xxxx.x_x \
     --privileged --network=host \
@@ -242,10 +242,10 @@ There are three main knobs:
 
 Options:
 
-- CVW_GIT: git clone address, only main branch supported
+- CVW_GIT: git clone address
-- CLEAN_CVW: declared with empty string to clone
+- CLEAN_CVW: clone CVW_GIT if enabled with `-e CLEAN_CVW=1`
-- BUILD_RISCOF: declared with empty string to rebuild RISCOF
+- BUILD_RISCOF: rebuild RISCOF if enabled with `-e BUILD_RISCOF=1`
-- RUN_QUESTA: declared with empty string to run vsim to check
+- RUN_QUESTA: run vsim to check if enabled with `-e RUN_QUESTA=1`
     - QUESTA: home folder for mounted QuestaSIM `/cad/mentor/questa_sim-xxxx.x_x` if enabled
     - for example, if your vsim is in `/cad/mentor/questa_sim-2023.4/questasim/bin/vsim` then your local QuestaSIM folder is `/cad/mentor/questa_sim-2023.4`, so you have to add `-v /cad/mentor/questa_sim-2023.4:/cad/mentor/questa_sim-xxxx.x_x -e RUN_QUESTA=1`
 
@@ -295,8 +295,7 @@ There are stages in the old Dockerfile:
 Description: permission problem in `/home/$USERNAME/cvw`.
 
 ```text
-$ podman run -v cvw_temp:/home/cad/cvw -e CLEAN_CVW= -e BUILD_RISCOF= -e RUN_QUESTA= -v /cad/mentor/que
+$ podman run -v cvw_temp:/home/cad/cvw -e CLEAN_CVW=1 -e BUILD_RISCOF=1 -e RUN_QUESTA=1 -v /cad/mentor/questa_sim-2023.4:/cad/mentor/questa_sim-xxxx.x_x --rm wallysoc/regression_wally                          
-sta_sim-2023.4:/cad/mentor/questa_sim-xxxx.x_x --rm wallysoc/regression_wally                          
 No CVW_GIT is provided                                                                                 
 rm: cannot remove '/home/cad/cvw': Device or resource busy                                             
 Cloning into '/home/cad/cvw'...                                                                        

docs/docker/run_regression.sh

@@ -17,12 +17,14 @@ if [ -z "${CVW_GIT}" ]; then
     export CVW_GIT="https://github.com/openhwgroup/cvw"
 else
     echo "Using customized CVW_GIT: ${CVW_GIT}"
+    # support specific branch now
+    export CVW_GIT=$(echo ${CVW_GIT} | sed -E "s/tree\// -b /g")
 fi
 
 git config --global http.version HTTP/1.1
 
 # if cvw is not available or CLEAN_CVW(empty string) is defined
-if [[ ! -f "/home/${USERNAME}/cvw/setup.sh" ]] || [[ -z "${CLEAN_CVW-x}" ]]; then
+if [[ ! -f "/home/${USERNAME}/cvw/setup.sh" ]] || [[ "${CLEAN_CVW}" -eq 1 ]]; then
     cd /home/${USERNAME} && rm -rf /home/${USERNAME}/cvw
     git clone --recurse-submodules  ${CVW_GIT} /home/${USERNAME}/cvw
     # if failed to clone submodules for some reason, please run `git submodule update`
@@ -46,11 +48,11 @@ export QUESTAPATH=/cad/mentor/questa_sim-xxxx.x_x/questasim/bin
 
 cd ${CVW_HOME}
 # build it only if BUILD_RISCOF is defined with empty string
-if [[ -z "${BUILD_RISCOF-x}" ]]; then
+if [[ "${BUILD_RISCOF}" -eq 1 ]]; then
     make install && make riscof && make testfloat
 fi
 
-if [[ -z "${RUN_QUESTA-x}" ]] ; then
+if [[ "${RUN_QUESTA}" -eq 1 ]] ; then
     if [ ! -f "${QUESTA}/questasim/bin/vsim" ]; then
         echo "Cannot find vsim with ${QUESTA}/questasim/bin/vsim"
     else
@@ -64,6 +66,7 @@ make coverage
 make benchmarks
 
 if [[ ! NO_VERILATOR -eq 1 ]]; then
-    cd ${CVW_HOME}/sim/verilator && verilator -GTEST="\"arch64i\"" -DVERILATOR=1 --timescale "1ns/1ns" --timing --binary --top-module testbench -I${CVW_HOME}/config/shared -I${CVW_HOME}/config/rv64gc ${CVW_HOME}/src/cvw.sv ${CVW_HOME}/testbench/testbench.sv ${CVW_HOME}/testbench/common/*.sv ${CVW_HOME}/src/*/*.sv ${CVW_HOME}/src/*/*/*.sv --relative-includes
+    make -C sim/verilator run
-    ${CVW_HOME}/sim/verilator/obj_dir/Vtestbench
+    # by default it runs the arch64i on rv64gc
+    cat ${CVW_HOME}/sim/verilator/logs/rv64gc_arch64i.log
 fi

fpga/generator/insert_debug_comment.sh

@@ -2,9 +2,9 @@
 ###########################################
 ## insert_debug_comment.sh
 ##
-## Written: Ross Thompson ross1728@gmail.com
+## Written: Rose Thompson ross1728@gmail.com
 ## Created: 20 January 2023
-## Modified: 20 January 2023
+## Modified: 16 April 2024
 ##
 ## A component of the CORE-V-WALLY configurable RISC-V project.
 ## https://github.com/openhwgroup/cvw
@@ -29,11 +29,21 @@
 # Then it processes them to add mark_debug on signals needed by the FPGA's ILA.
 copiedDir="../src/CopiedFiles_do_not_add_to_repo"
 while read line; do
-    readarray -d ":" -t StrArray <<< "$line"
+    # older versions of bash are incompatible with readarray -d :(
-    file="${copiedDir}/${StrArray[0]}"
+    #readarray -d ":" -t StrArray <<< "$line"
-    signal=`echo "${StrArray[1]}" | awk '{$1=$1};1'`
+    #file="${copiedDir}/${StrArray[0]}"
+    #signal=`echo "${StrArray[1]}" | awk '{$1=$1};1'`
+    fileName=`echo $line | cut -d  ":" -f 1`
+    file=${copiedDir}/$fileName
+    signal=`echo $line | cut -d  ":" -f 2`
+    echo $file
+    echo $signal
     readarray -d " " -t SigArray <<< $signal
-    sigType=`echo "${SigArray[0]}" | awk '{$1=$1};1'`
+    sigType=`echo $signal | cut -d " " -f 1`
-    sigName=`echo "${SigArray[1]}" | awk '{$1=$1};1'`
+    sigType=`echo $sigType | awk '{$1=$1};1'`
+    sigName=`echo $signal | cut -d " " -f 2`
+    sigName=`echo $sigName | awk '{$1=$1};1'`
+    #sigType=`echo "${SigArray[0]}" | awk '{$1=$1};1'`
+    #sigName=`echo "${SigArray[1]}" | awk '{$1=$1};1'`
     find $copiedDir -wholename $file | xargs sed -i "s/\(.*${sigType}.*${sigName}\)/(\* mark_debug = \"true\" \*)\1/g" 
 done < ../constraints/marked_debug.txt

testbench/testbench.sv

@@ -39,6 +39,7 @@ import "DPI-C" function string getenvval(input string env_name);
 `else
 import "DPI-C" function string getenv(input string env_name);
 `endif
+import "DPI-C" function int system(input string env_name);
 
 module testbench;
   /* verilator lint_off WIDTHTRUNC */
@@ -326,6 +327,9 @@ module testbench;
     assign EcallFaultM = dut.core.priv.priv.EcallFaultM;
   else
     assign EcallFaultM = 0;
+  
+  // this is an unused integer for the return value of `system`
+  int unused_int;
   always @(posedge clk) begin
     ////////////////////////////////////////////////////////////////////////////////
     // Verify the test ran correctly by checking the memory against a known signature.
@@ -352,7 +356,7 @@ module testbench;
         bootmemfilename = {RISCV_DIR, "/linux-testvectors/bootmem.bin"};
         uartoutfilename = {"logs/", TEST, "_uart.out"};
         rmCmd = {"rm -f ", uartoutfilename};
-        $system(rmCmd); // Delete existing UARToutfile
+        unused_int = system(rmCmd); // Delete existing UARToutfile
       end
       else            memfilename = {pathname, tests[test], ".elf.memfile"};
       if (riscofTest) begin