From c306884e2c08e66aab6ff944a42a58b7a2ec51d0 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 1 Nov 2021 08:48:46 -0700 Subject: [PATCH 01/12] Adding custom Wally test infrastructure --- .../{wally-I.py => wally-I-PIPELINE.py} | 2 +- .../rv32i_m/I/src/WALLY-PIPELINE.S | 82 +++++++++++++++++++ .../riscv-test-suite/rv64i_m/D/Makefile | 3 + .../riscv-test-suite/rv64i_m/D/Makefrag | 35 ++++++++ .../rv64i_m/I/src/WALLY-PIPELINE.S | 82 +++++++++++++++++++ .../regression/regression-wally.py | 2 +- wally-pipelined/testbench/testbench.sv | 51 ++---------- wally-pipelined/testbench/tests.vh | 30 ++++++- 8 files changed, 242 insertions(+), 45 deletions(-) rename tests/testgen/{wally-I.py => wally-I-PIPELINE.py} (99%) create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-PIPELINE.S create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D/Makefile create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D/Makefrag create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-PIPELINE.S diff --git a/tests/testgen/wally-I.py b/tests/testgen/wally-I-PIPELINE.py similarity index 99% rename from tests/testgen/wally-I.py rename to tests/testgen/wally-I-PIPELINE.py index b186e21c5..80ac853b1 100755 --- a/tests/testgen/wally-I.py +++ b/tests/testgen/wally-I-PIPELINE.py @@ -1,6 +1,6 @@ #!/usr/bin/python3 ################################## -# wally-I.py +# wally-I-PIPELINE.py # # David_Harris@hmc.edu 27 October 2021 # diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-PIPELINE.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-PIPELINE.S new file mode 100644 index 000000000..28d36e3ed --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-PIPELINE.S @@ -0,0 +1,82 @@ +/////////////////////////////////////////// +// ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-PIPELINE.S +// David_Harris@hmc.edu +// Created 2021-11-01 08:46:04.665699// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64I") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",add) + +RVTEST_SIGBASE( x8,signature_x8_1) +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN + + +signature_x8_0: + .fill 0*(XLEN/32),4,0xdeadbeef + + +signature_x8_1: + .fill 19*(XLEN/32),4,0xdeadbeef + + +signature_x1_0: + .fill 256*(XLEN/32),4,0xdeadbeef + + +signature_x1_1: + .fill 256*(XLEN/32),4,0xdeadbeef + + +signature_x1_2: + .fill 148*(XLEN/32),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine + +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef + +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*(XLEN/32),4,0xdeadbeef + +#endif + +RVMODEL_DATA_END +// ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-PIPELINE.S +// David_Harris@hmc.edu diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D/Makefile b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D/Makefile new file mode 100644 index 000000000..a474441d6 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D/Makefile @@ -0,0 +1,3 @@ +include ../../Makefile.include + +$(eval $(call compile_template,-march=rv64id -mabi=lp64 -DXLEN=$(XLEN))) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D/Makefrag new file mode 100644 index 000000000..261a9a852 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D/Makefrag @@ -0,0 +1,35 @@ +# RISC-V Architecture Test RV64IM Makefrag +# +# Copyright (c) 2018, Imperas Software Ltd. +# Copyright (c) 2020, InCore Semiconductors. Pvt. Ltd. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of the Imperas Software Ltd. nor the +# names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Description: Makefrag for RV64IM architectural tests + +rv64im_sc_tests = \ + +rv64im_tests = $(addsuffix .elf, $(rv64im_sc_tests)) + +target_tests += $(rv64im_tests) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-PIPELINE.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-PIPELINE.S new file mode 100644 index 000000000..e7d29cc8d --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-PIPELINE.S @@ -0,0 +1,82 @@ +/////////////////////////////////////////// +// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-PIPELINE.S +// David_Harris@hmc.edu +// Created 2021-11-01 08:46:04.668632// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64I") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",add) + +RVTEST_SIGBASE( x8,signature_x8_1) +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN + + +signature_x8_0: + .fill 0*(XLEN/32),4,0xdeadbeef + + +signature_x8_1: + .fill 19*(XLEN/32),4,0xdeadbeef + + +signature_x1_0: + .fill 256*(XLEN/32),4,0xdeadbeef + + +signature_x1_1: + .fill 256*(XLEN/32),4,0xdeadbeef + + +signature_x1_2: + .fill 148*(XLEN/32),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine + +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef + +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*(XLEN/32),4,0xdeadbeef + +#endif + +RVMODEL_DATA_END +// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-PIPELINE.S +// David_Harris@hmc.edu diff --git a/wally-pipelined/regression/regression-wally.py b/wally-pipelined/regression/regression-wally.py index 79532c5c8..49ca87129 100755 --- a/wally-pipelined/regression/regression-wally.py +++ b/wally-pipelined/regression/regression-wally.py @@ -41,7 +41,7 @@ def getBuildrootTC(short): BRgrepstr=str(MAX_EXPECTED)+" instructions" return TestCase(name="buildroot",cmd=BRcmd,grepstr=BRgrepstr) -tests64 = ["arch64i", "arch64priv", "arch64c", "arch64m", "imperas64i", "imperas64p", "imperas64mmu", "imperas64f", "imperas64d", "imperas64m", "imperas64a", "imperas64c"] #, "testsBP64"] +tests64 = ["wally64i", "arch64i", "arch64priv", "arch64c", "arch64m", "imperas64i", "imperas64p", "imperas64mmu", "imperas64f", "imperas64d", "imperas64m", "imperas64a", "imperas64c"] #, "testsBP64"] for test in tests64: tc = TestCase( name=test, diff --git a/wally-pipelined/testbench/testbench.sv b/wally-pipelined/testbench/testbench.sv index 8c25f1549..13ba7e16a 100644 --- a/wally-pipelined/testbench/testbench.sv +++ b/wally-pipelined/testbench/testbench.sv @@ -94,7 +94,9 @@ logic [3:0] dummy; "imperas64c": if (`C_SUPPORTED) tests = imperas64c; else tests = imperas64iNOc; "testsBP64": tests = testsBP64; - // *** add arch f and d tests, peripheral tests + "wally64i": tests = wally64i; + "wally64priv": tests = wally64priv; + "wally64periph": tests = wally64periph; endcase end else begin // RV32 case (TEST) @@ -111,51 +113,15 @@ logic [3:0] dummy; "imperas32a": if (`A_SUPPORTED) tests = imperas32a; "imperas32c": if (`C_SUPPORTED) tests = imperas32c; else tests = imperas32iNOc; - // ***add arch f and d tests + "wally32i": tests = wally32i; + "wally32priv": tests = wally32priv; + "wally32periph": tests = wally32periph; endcase end if (tests.size() == 1) begin $display("TEST %s not supported in this configuration", TEST); $stop; end - //if (TEST == "arch-64m") //tests = {archtests64m}; - /* if (`XLEN == 64) begin // RV64 - if (`TESTSBP) begin - tests = testsBP64; - // testsbp should not run the other tests. It starts at address 0 rather than - // 0x8000_0000, the next if must remain an else if. - end else if (TESTSPERIPH) - tests = imperastests64periph; - else if (TESTSPRIV) - tests = imperastests64p; - else begin - tests = {imperastests64p,imperastests64i, imperastests64periph}; - if (`C_SUPPORTED) tests = {tests, imperastests64ic}; - else tests = {tests, imperastests64iNOc}; - if (`F_SUPPORTED) tests = {imperastests64f, tests}; - if (`D_SUPPORTED) tests = {imperastests64d, tests}; - if (`MEM_VIRTMEM) tests = {imperastests64mmu, tests}; - if (`A_SUPPORTED) tests = {imperastests64a, tests}; - if (`M_SUPPORTED) tests = {imperastests64m, tests}; - end - //tests = {imperastests64a, tests}; - end else begin // RV32 - // *** add the 32 bit bp tests - if (TESTSPERIPH) - tests = imperastests32periph; - else if (TESTSPRIV) - tests = imperastests32p; - else begin - tests = {archtests32i, imperastests32i, imperastests32p};//,imperastests32periph}; *** broken at the moment - if (`C_SUPPORTED) tests = {tests, imperastests32ic}; - else tests = {tests, imperastests32iNOc}; - if (`F_SUPPORTED) tests = {imperastests32f, tests}; - if (`MEM_VIRTMEM) tests = {imperastests32mmu, tests}; - if (`A_SUPPORTED) tests = {imperastests32a, tests}; - if (`M_SUPPORTED) tests = {imperastests32m, tests}; - tests = {archtests32i}; - end - end */ end string signame, memfilename, pathname; @@ -203,9 +169,10 @@ logic [3:0] dummy; end end // read test vectors into memory - if (tests[0] == `IMPERASTEST) + pathname = tvpaths[tests[0].atoi()]; +/* if (tests[0] == `IMPERASTEST) pathname = tvpaths[0]; - else pathname = tvpaths[1]; + else pathname = tvpaths[1]; */ memfilename = {pathname, tests[test], ".elf.memfile"}; $readmemh(memfilename, dut.uncore.dtim.RAM); ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"}; diff --git a/wally-pipelined/testbench/tests.vh b/wally-pipelined/testbench/tests.vh index 42b1fc0b5..b10be8765 100644 --- a/wally-pipelined/testbench/tests.vh +++ b/wally-pipelined/testbench/tests.vh @@ -25,10 +25,12 @@ `define IMPERASTEST "0" `define RISCVARCHTEST "1" +`define WALLYTEST "2" string tvpaths[] = '{ "../../tests/imperas-riscv-tests/work/", - "../../addins/riscv-arch-test/work/" + "../../addins/riscv-arch-test/work/", + "../../tests/wally-riscv-arch-test/work/" }; string imperas32mmu[] = '{ @@ -1067,4 +1069,30 @@ string imperas32f[] = '{ "rv32i_m/I/xori-01", "4010" }; + string wally64i[] = '{ + `WALLYTEST, + "rv64i_m/I/add-01", "9010" +// "rv64i_m/I/pipeline-01", "9010" + }; + + string wally64priv[] = '{ + `WALLYTEST + }; + + string wally64periph[] = '{ + `WALLYTEST + }; + +string wally32i[] = '{ + `WALLYTEST, + "rv64i_m/I/pipeline-01", "9010" + }; + + string wally32priv[] = '{ + `WALLYTEST + }; + + string wally32periph[] = '{ + `WALLYTEST + }; From 4b57af9cffa49964ad2dab7688bc423aa520cbc5 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 1 Nov 2021 12:44:35 -0700 Subject: [PATCH 02/12] PIPELINE test running --- .../{wally-I-PIPELINE.py => PIPELINE.py} | 17 +++- tests/testgen/testgen_footer.S | 1 + tests/wally-riscv-arch-test/Makefile | 2 +- .../rv32i_m/I/src/WALLY-PIPELINE.S | 9 +- .../riscv-test-suite/rv64i_m/I/Makefrag | 1 + .../rv64i_m/I/src/WALLY-PIPELINE.S | 82 ------------------- wally-pipelined/src/fpu/fpudivsqrtrecur.sv | 2 +- wally-pipelined/src/muldiv/div.sv | 9 +- wally-pipelined/testbench/tests.vh | 4 +- 9 files changed, 36 insertions(+), 91 deletions(-) rename tests/testgen/{wally-I-PIPELINE.py => PIPELINE.py} (90%) delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-PIPELINE.S diff --git a/tests/testgen/wally-I-PIPELINE.py b/tests/testgen/PIPELINE.py similarity index 90% rename from tests/testgen/wally-I-PIPELINE.py rename to tests/testgen/PIPELINE.py index 80ac853b1..e6b8bde29 100755 --- a/tests/testgen/wally-I-PIPELINE.py +++ b/tests/testgen/PIPELINE.py @@ -1,6 +1,6 @@ #!/usr/bin/python3 ################################## -# wally-I-PIPELINE.py +# PIPELINE.py # # David_Harris@hmc.edu 27 October 2021 # @@ -108,7 +108,7 @@ for xlen in xlens: storecmd = "sd" wordsize = 8 pathname = "../wally-riscv-arch-test/riscv-test-suite/rv" + str(xlen) + "i_m/I/" - fname = pathname + "src/WALLY-PIPELINE.S" + fname = pathname + "src/PIPELINE.S" testnum = 0 # print custom header part @@ -126,6 +126,19 @@ for xlen in xlens: for line in h: f.write(line) + maxreg = 5 + for i in range(1): + instr = instrs[randint(0,len(instrs)-1)] + reg1 = randint(0,maxreg) + reg2 = randint(0,maxreg) + reg3 = randint(1,maxreg) + line = instr + " x" +str(reg3) + ", x" + str(reg1) + ", x" + str(reg2) + "\n" + f.write(line) + + for i in range(1,maxreg+1): + line = storecmd + " x" + str(i) + ", " + str(wordsize*(i-1)) + "(x8)\n" + f.write(line) + # print directed and random test vectors # for a in corners: # for b in corners: diff --git a/tests/testgen/testgen_footer.S b/tests/testgen/testgen_footer.S index b0137b792..5f72c5b49 100644 --- a/tests/testgen/testgen_footer.S +++ b/tests/testgen/testgen_footer.S @@ -1,3 +1,4 @@ +#endif RVTEST_CODE_END RVMODEL_HALT diff --git a/tests/wally-riscv-arch-test/Makefile b/tests/wally-riscv-arch-test/Makefile index 8e817231d..0f6f2be08 100644 --- a/tests/wally-riscv-arch-test/Makefile +++ b/tests/wally-riscv-arch-test/Makefile @@ -87,7 +87,7 @@ simulate: run -C $(SUITEDIR) verify: simulate - riscv-test-env/verify.sh +# riscv-test-env/verify.sh # dmh 1 November 2021 removed because these tests don't have expected values postverify: ifeq ($(wildcard $(TARGETDIR)/$(RISCV_TARGET)/postverify.sh),) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-PIPELINE.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-PIPELINE.S index 28d36e3ed..1fd7866e1 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-PIPELINE.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-PIPELINE.S @@ -1,7 +1,7 @@ /////////////////////////////////////////// // ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-PIPELINE.S // David_Harris@hmc.edu -// Created 2021-11-01 08:46:04.665699// +// Created 2021-11-01 11:43:39.219968// // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // // Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation @@ -32,6 +32,13 @@ RVTEST_CODE_BEGIN RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",add) RVTEST_SIGBASE( x8,signature_x8_1) +AND x1, x3, x3 +sw x1, 0(x8) +sw x2, 4(x8) +sw x3, 8(x8) +sw x4, 12(x8) +sw x5, 16(x8) +#endif RVTEST_CODE_END RVMODEL_HALT diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/Makefrag index f85d344df..d14e2c26b 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/Makefrag +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/Makefrag @@ -29,6 +29,7 @@ rv64i_sc_tests = \ add-01 \ + PIPELINE \ diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-PIPELINE.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-PIPELINE.S deleted file mode 100644 index e7d29cc8d..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-PIPELINE.S +++ /dev/null @@ -1,82 +0,0 @@ -/////////////////////////////////////////// -// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-PIPELINE.S -// David_Harris@hmc.edu -// Created 2021-11-01 08:46:04.668632// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation -// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, -// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software -// is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT -// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -/////////////////////////////////////////// - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64I") - -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - -RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",add) - -RVTEST_SIGBASE( x8,signature_x8_1) -RVTEST_CODE_END -RVMODEL_HALT - -RVTEST_DATA_BEGIN -.align 4 -rvtest_data: -.word 0xbabecafe -RVTEST_DATA_END - -RVMODEL_DATA_BEGIN - - -signature_x8_0: - .fill 0*(XLEN/32),4,0xdeadbeef - - -signature_x8_1: - .fill 19*(XLEN/32),4,0xdeadbeef - - -signature_x1_0: - .fill 256*(XLEN/32),4,0xdeadbeef - - -signature_x1_1: - .fill 256*(XLEN/32),4,0xdeadbeef - - -signature_x1_2: - .fill 148*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -RVMODEL_DATA_END -// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-PIPELINE.S -// David_Harris@hmc.edu diff --git a/wally-pipelined/src/fpu/fpudivsqrtrecur.sv b/wally-pipelined/src/fpu/fpudivsqrtrecur.sv index 0d1b89ff2..c5a646456 100644 --- a/wally-pipelined/src/fpu/fpudivsqrtrecur.sv +++ b/wally-pipelined/src/fpu/fpudivsqrtrecur.sv @@ -55,7 +55,7 @@ module fpudivsqrtrecur ( // Special Cases // *** shift to handle denorms in hardware - assign FDivSqrtResSign = FDivE & (XSgnE ^ YSgnE); // Sign is negative for division if inputs have opposite signs + assign FDivSqrtResSgn = FDivE & (XSgnE ^ YSgnE); // Sign is negative for division if inputs have opposite signs always_comb begin if (FSqrtE & XSgnE | FDivE & XZeroE & YZeroE | XNaNE | FDivE & YNaNE) FDivSqrtResM = 0; // ***replace with NAN; // *** which one diff --git a/wally-pipelined/src/muldiv/div.sv b/wally-pipelined/src/muldiv/div.sv index b299af032..d7f311a3f 100755 --- a/wally-pipelined/src/muldiv/div.sv +++ b/wally-pipelined/src/muldiv/div.sv @@ -64,7 +64,10 @@ module intdiv #(parameter WIDTH=64) logic [WIDTH-1:0] QT, remT; logic D_NegOne; logic Max_N; - + + logic otfzerov; + logic tcQ; + logic tcR; // Check if negative (two's complement) // If so, convert to positive @@ -182,7 +185,9 @@ module divide4 #(parameter WIDTH=64) logic CshiftQ, CshiftQM; logic [WIDTH+3:0] rem1, rem2, rem3; logic [WIDTH+3:0] SumR, CarryR; - logic [WIDTH:0] Qt; + logic [WIDTH:0] Qt; + + logic ulp; // Create one's complement values of Divisor (for q*D) assign divi1 = {3'h0, op2, 1'b0}; diff --git a/wally-pipelined/testbench/tests.vh b/wally-pipelined/testbench/tests.vh index b10be8765..e897819f7 100644 --- a/wally-pipelined/testbench/tests.vh +++ b/wally-pipelined/testbench/tests.vh @@ -1071,8 +1071,8 @@ string imperas32f[] = '{ string wally64i[] = '{ `WALLYTEST, - "rv64i_m/I/add-01", "9010" -// "rv64i_m/I/pipeline-01", "9010" + "rv64i_m/I/add-01", "9010", + "rv64i_m/I/PIPELINE", "2010" }; string wally64priv[] = '{ From 910957704b26638233c79954e91f6e3b2e5a15e3 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 1 Nov 2021 13:17:49 -0700 Subject: [PATCH 03/12] Add3d wally32i test --- tests/testgen/PIPELINE.py | 8 +- .../riscv-test-suite/rv32i_m/I/Makefrag | 2 +- .../rv32i_m/I/src/WALLY-PIPELINE.S | 89 ------------------- .../regression/regression-wally.py | 2 +- wally-pipelined/testbench/tests.vh | 4 +- 5 files changed, 8 insertions(+), 97 deletions(-) delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-PIPELINE.S diff --git a/tests/testgen/PIPELINE.py b/tests/testgen/PIPELINE.py index e6b8bde29..6432bb023 100755 --- a/tests/testgen/PIPELINE.py +++ b/tests/testgen/PIPELINE.py @@ -88,10 +88,10 @@ def writeVector(a, b, storecmd, xlen): ################################## # change these to suite your tests -instrs = ["ADD", "SUB", "SLT", "SLTU", "XOR", "OR", "AND"] +instrs = ["ADD"] # "SUB", "XOR", "OR", "AND", "SLT", "SLTU", ] author = "David_Harris@hmc.edu" xlens = [32, 64] -numrand = 100 +numrand = 1000 # setup seed(0) # make tests reproducible @@ -127,10 +127,10 @@ for xlen in xlens: f.write(line) maxreg = 5 - for i in range(1): + for i in range(numrand): instr = instrs[randint(0,len(instrs)-1)] reg1 = randint(0,maxreg) - reg2 = randint(0,maxreg) + reg2 = randint(1,maxreg) reg3 = randint(1,maxreg) line = instr + " x" +str(reg3) + ", x" + str(reg1) + ", x" + str(reg2) + "\n" f.write(line) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/Makefrag index e2cdf44da..49f87b201 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/Makefrag +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/Makefrag @@ -28,7 +28,7 @@ # Description: Makefrag for RV32I architectural tests rv32i_sc_tests = \ - WALLY-PIPELINE \ + PIPELINE \ rv32i_tests = $(addsuffix .elf, $(rv32i_sc_tests)) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-PIPELINE.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-PIPELINE.S deleted file mode 100644 index 1fd7866e1..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-PIPELINE.S +++ /dev/null @@ -1,89 +0,0 @@ -/////////////////////////////////////////// -// ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-PIPELINE.S -// David_Harris@hmc.edu -// Created 2021-11-01 11:43:39.219968// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation -// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, -// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software -// is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT -// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -/////////////////////////////////////////// - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64I") - -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - -RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",add) - -RVTEST_SIGBASE( x8,signature_x8_1) -AND x1, x3, x3 -sw x1, 0(x8) -sw x2, 4(x8) -sw x3, 8(x8) -sw x4, 12(x8) -sw x5, 16(x8) -#endif -RVTEST_CODE_END -RVMODEL_HALT - -RVTEST_DATA_BEGIN -.align 4 -rvtest_data: -.word 0xbabecafe -RVTEST_DATA_END - -RVMODEL_DATA_BEGIN - - -signature_x8_0: - .fill 0*(XLEN/32),4,0xdeadbeef - - -signature_x8_1: - .fill 19*(XLEN/32),4,0xdeadbeef - - -signature_x1_0: - .fill 256*(XLEN/32),4,0xdeadbeef - - -signature_x1_1: - .fill 256*(XLEN/32),4,0xdeadbeef - - -signature_x1_2: - .fill 148*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -RVMODEL_DATA_END -// ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-PIPELINE.S -// David_Harris@hmc.edu diff --git a/wally-pipelined/regression/regression-wally.py b/wally-pipelined/regression/regression-wally.py index 49ca87129..ada9fe383 100755 --- a/wally-pipelined/regression/regression-wally.py +++ b/wally-pipelined/regression/regression-wally.py @@ -49,7 +49,7 @@ for test in tests64: grepstr="All tests ran without failures") configs.append(tc) #tests32 = ["arch32i", "arch32priv", "arch32c", "arch32m", "arch32f", "imperas32i", "imperas32p", "imperas32mmu", "imperas32f", "imperas32m", "imperas32a", "imperas32c"] -tests32 = ["arch32i", "arch32priv", "arch32c", "arch32m", "imperas32i", "imperas32p", "imperas32mmu", "imperas32f", "imperas32m", "imperas32a", "imperas32c"] +tests32 = ["wally32i", "arch32i", "arch32priv", "arch32c", "arch32m", "imperas32i", "imperas32p", "imperas32mmu", "imperas32f", "imperas32m", "imperas32a", "imperas32c"] for test in tests32: tc = TestCase( name=test, diff --git a/wally-pipelined/testbench/tests.vh b/wally-pipelined/testbench/tests.vh index e897819f7..7e33ef68c 100644 --- a/wally-pipelined/testbench/tests.vh +++ b/wally-pipelined/testbench/tests.vh @@ -1072,7 +1072,7 @@ string imperas32f[] = '{ string wally64i[] = '{ `WALLYTEST, "rv64i_m/I/add-01", "9010", - "rv64i_m/I/PIPELINE", "2010" + "rv64i_m/I/PIPELINE", "3010" }; string wally64priv[] = '{ @@ -1085,7 +1085,7 @@ string imperas32f[] = '{ string wally32i[] = '{ `WALLYTEST, - "rv64i_m/I/pipeline-01", "9010" + "rv32i_m/I/PIPELINE", "3010" }; string wally32priv[] = '{ From 0c829dd62cd103a113f60f89dcaf563f09b94870 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 1 Nov 2021 13:24:18 -0700 Subject: [PATCH 04/12] simplified header and footer --- tests/testgen/testgen_footer.S | 1 - tests/testgen/testgen_header.S | 5 ----- 2 files changed, 6 deletions(-) diff --git a/tests/testgen/testgen_footer.S b/tests/testgen/testgen_footer.S index 5f72c5b49..b0137b792 100644 --- a/tests/testgen/testgen_footer.S +++ b/tests/testgen/testgen_footer.S @@ -1,4 +1,3 @@ -#endif RVTEST_CODE_END RVMODEL_HALT diff --git a/tests/testgen/testgen_header.S b/tests/testgen/testgen_header.S index 3b3bd6876..df9f0dcfd 100644 --- a/tests/testgen/testgen_header.S +++ b/tests/testgen/testgen_header.S @@ -16,7 +16,6 @@ #include "model_test.h" #include "arch_test.h" -RVTEST_ISA("RV64I") .section .text.init .globl rvtest_entry_point @@ -24,8 +23,4 @@ rvtest_entry_point: RVMODEL_BOOT RVTEST_CODE_BEGIN -#ifdef TEST_CASE_1 - -RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",add) - RVTEST_SIGBASE( x8,signature_x8_1) From db268471b6e6ca734ce90378433ce27c6a3c4e9f Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 1 Nov 2021 13:36:07 -0700 Subject: [PATCH 05/12] added some missing files --- .../riscv-test-suite/rv32i_m/I/src/PIPELINE.S | 1082 +++++++++++++++++ .../riscv-test-suite/rv64i_m/I/src/PIPELINE.S | 1082 +++++++++++++++++ 2 files changed, 2164 insertions(+) create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/PIPELINE.S create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/PIPELINE.S diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/PIPELINE.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/PIPELINE.S new file mode 100644 index 000000000..370fb8f29 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/PIPELINE.S @@ -0,0 +1,1082 @@ +/////////////////////////////////////////// +// ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/PIPELINE.S +// David_Harris@hmc.edu +// Created 2021-11-01 13:22:54.967257// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "model_test.h" +#include "arch_test.h" + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +RVTEST_SIGBASE( x8,signature_x8_1) +ADD x3, x3, x1 +ADD x4, x3, x3 +ADD x5, x4, x2 +ADD x1, x2, x2 +ADD x2, x4, x5 +ADD x3, x0, x1 +ADD x3, x4, x1 +ADD x2, x2, x5 +ADD x3, x3, x5 +ADD x1, x4, x1 +ADD x5, x5, x1 +ADD x3, x2, x2 +ADD x2, x1, x5 +ADD x4, x1, x5 +ADD x5, x0, x3 +ADD x5, x0, x3 +ADD x5, x5, x1 +ADD x5, x4, x2 +ADD x5, x3, x1 +ADD x2, x2, x5 +ADD x2, x1, x2 +ADD x4, x4, x3 +ADD x2, x0, x2 +ADD x4, x0, x5 +ADD x2, x4, x2 +ADD x4, x4, x3 +ADD x1, x5, x3 +ADD x4, x4, x1 +ADD x1, x1, x2 +ADD x3, x0, x2 +ADD x1, x2, x4 +ADD x1, x1, x2 +ADD x2, x0, x1 +ADD x3, x3, x1 +ADD x1, x0, x5 +ADD x4, x1, x1 +ADD x1, x5, x1 +ADD x3, x4, x1 +ADD x3, x1, x1 +ADD x1, x3, x2 +ADD x1, x0, x5 +ADD x3, x1, x3 +ADD x2, x4, x2 +ADD x2, x5, x2 +ADD x1, x4, x3 +ADD x1, x5, x2 +ADD x5, x5, x4 +ADD x4, x5, x3 +ADD x1, x1, x5 +ADD x3, x5, x1 +ADD x2, x4, x3 +ADD x5, x3, x3 +ADD x5, x5, x3 +ADD x4, x5, x3 +ADD x1, x5, x1 +ADD x2, x5, x3 +ADD x4, x1, x4 +ADD x5, x0, x4 +ADD x2, x5, x1 +ADD x2, x0, x3 +ADD x5, x4, x4 +ADD x3, x0, x4 +ADD x4, x3, x1 +ADD x2, x4, x1 +ADD x3, x3, x4 +ADD x1, x1, x1 +ADD x5, x1, x1 +ADD x2, x2, x3 +ADD x1, x3, x4 +ADD x1, x2, x4 +ADD x3, x1, x5 +ADD x1, x1, x3 +ADD x3, x0, x2 +ADD x1, x2, x5 +ADD x4, x5, x4 +ADD x2, x4, x2 +ADD x1, x4, x3 +ADD x3, x1, x3 +ADD x3, x2, x1 +ADD x2, x0, x3 +ADD x3, x4, x3 +ADD x3, x4, x2 +ADD x1, x3, x2 +ADD x1, x1, x5 +ADD x3, x3, x3 +ADD x5, x0, x1 +ADD x3, x3, x3 +ADD x4, x3, x1 +ADD x3, x0, x3 +ADD x4, x1, x5 +ADD x2, x0, x1 +ADD x1, x0, x4 +ADD x5, x3, x5 +ADD x5, x3, x4 +ADD x3, x3, x1 +ADD x2, x2, x5 +ADD x1, x1, x3 +ADD x5, x5, x1 +ADD x1, x5, x2 +ADD x2, x3, x3 +ADD x2, x1, x5 +ADD x4, x1, x4 +ADD x1, x4, x2 +ADD x4, x1, x5 +ADD x3, x4, x4 +ADD x5, x3, x2 +ADD x3, x0, x3 +ADD x2, x0, x5 +ADD x4, x4, x2 +ADD x1, x5, x4 +ADD x1, x4, x1 +ADD x3, x1, x1 +ADD x2, x3, x3 +ADD x3, x5, x4 +ADD x1, x4, x5 +ADD x5, x5, x5 +ADD x2, x5, x4 +ADD x4, x4, x5 +ADD x5, x3, x5 +ADD x2, x0, x1 +ADD x3, x4, x5 +ADD x3, x0, x4 +ADD x4, x3, x4 +ADD x2, x1, x2 +ADD x1, x5, x3 +ADD x2, x3, x4 +ADD x2, x4, x1 +ADD x5, x3, x1 +ADD x1, x3, x4 +ADD x1, x3, x2 +ADD x2, x4, x5 +ADD x3, x0, x5 +ADD x1, x3, x4 +ADD x5, x4, x4 +ADD x5, x5, x1 +ADD x3, x1, x4 +ADD x1, x4, x2 +ADD x2, x3, x3 +ADD x1, x2, x1 +ADD x1, x3, x3 +ADD x5, x1, x1 +ADD x1, x4, x3 +ADD x4, x3, x5 +ADD x1, x0, x4 +ADD x1, x3, x2 +ADD x1, x3, x4 +ADD x1, x2, x3 +ADD x3, x0, x1 +ADD x2, x2, x3 +ADD x1, x1, x3 +ADD x2, x1, x1 +ADD x3, x5, x1 +ADD x5, x5, x1 +ADD x4, x1, x2 +ADD x3, x3, x3 +ADD x3, x0, x2 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x4, x4 +ADD x2, x5, x4 +ADD x1, x2, x1 +ADD x1, x1, x3 +ADD x2, x5, x1 +ADD x5, x3, x2 +ADD x4, x4, x2 +ADD x1, x2, x5 +ADD x5, x2, x3 +ADD x1, x2, x3 +ADD x1, x1, x3 +ADD x2, x4, x3 +ADD x3, x2, x3 +ADD x3, x2, x4 +ADD x5, x0, x3 +ADD x4, x0, x4 +ADD x4, x0, x4 +ADD x1, x3, x1 +ADD x2, x1, x1 +ADD x5, x1, x4 +ADD x4, x3, x5 +ADD x4, x1, x2 +ADD x3, x1, x3 +ADD x5, x3, x1 +ADD x2, x4, x5 +ADD x5, x3, x5 +ADD x3, x4, x3 +ADD x5, x0, x1 +ADD x2, x1, x4 +ADD x5, x2, x1 +ADD x4, x0, x1 +ADD x3, x0, x5 +ADD x3, x5, x5 +ADD x1, x5, x2 +ADD x2, x5, x3 +ADD x3, x5, x4 +ADD x5, x1, x1 +ADD x1, x2, x5 +ADD x2, x3, x2 +ADD x4, x1, x2 +ADD x2, x1, x2 +ADD x5, x2, x5 +ADD x1, x5, x4 +ADD x3, x4, x5 +ADD x1, x3, x3 +ADD x4, x4, x2 +ADD x1, x4, x3 +ADD x4, x1, x5 +ADD x4, x2, x3 +ADD x3, x1, x1 +ADD x2, x2, x4 +ADD x3, x2, x2 +ADD x5, x2, x5 +ADD x3, x5, x2 +ADD x1, x3, x1 +ADD x2, x0, x1 +ADD x3, x0, x1 +ADD x4, x1, x2 +ADD x3, x1, x3 +ADD x4, x5, x3 +ADD x3, x0, x4 +ADD x1, x0, x5 +ADD x1, x3, x2 +ADD x2, x4, x5 +ADD x2, x2, x2 +ADD x5, x0, x2 +ADD x4, x5, x1 +ADD x2, x4, x4 +ADD x4, x2, x3 +ADD x4, x5, x1 +ADD x2, x2, x3 +ADD x3, x1, x5 +ADD x3, x5, x4 +ADD x1, x3, x4 +ADD x5, x4, x3 +ADD x5, x0, x5 +ADD x4, x5, x1 +ADD x4, x5, x1 +ADD x1, x3, x1 +ADD x3, x5, x1 +ADD x5, x5, x2 +ADD x2, x3, x3 +ADD x2, x4, x3 +ADD x3, x1, x2 +ADD x5, x4, x1 +ADD x3, x2, x3 +ADD x4, x2, x4 +ADD x2, x1, x1 +ADD x3, x3, x2 +ADD x3, x5, x4 +ADD x4, x0, x5 +ADD x2, x1, x5 +ADD x5, x5, x2 +ADD x5, x4, x5 +ADD x3, x3, x3 +ADD x3, x0, x4 +ADD x5, x4, x5 +ADD x4, x2, x2 +ADD x2, x0, x5 +ADD x1, x2, x4 +ADD x2, x5, x5 +ADD x2, x2, x5 +ADD x4, x5, x3 +ADD x5, x5, x2 +ADD x4, x2, x2 +ADD x2, x4, x4 +ADD x2, x4, x1 +ADD x4, x3, x1 +ADD x4, x2, x3 +ADD x1, x4, x3 +ADD x1, x0, x4 +ADD x4, x1, x4 +ADD x1, x5, x4 +ADD x2, x2, x5 +ADD x4, x2, x1 +ADD x1, x4, x2 +ADD x3, x4, x3 +ADD x1, x0, x2 +ADD x1, x0, x3 +ADD x3, x3, x2 +ADD x5, x5, x2 +ADD x5, x3, x3 +ADD x2, x1, x2 +ADD x5, x5, x1 +ADD x2, x4, x4 +ADD x1, x4, x1 +ADD x3, x2, x2 +ADD x3, x5, x3 +ADD x5, x1, x4 +ADD x2, x0, x5 +ADD x2, x2, x1 +ADD x4, x4, x2 +ADD x2, x5, x3 +ADD x5, x4, x1 +ADD x1, x4, x3 +ADD x5, x0, x4 +ADD x3, x4, x4 +ADD x1, x4, x3 +ADD x2, x2, x1 +ADD x5, x0, x3 +ADD x1, x0, x4 +ADD x5, x3, x1 +ADD x4, x2, x1 +ADD x5, x3, x3 +ADD x5, x5, x3 +ADD x1, x3, x2 +ADD x4, x2, x2 +ADD x1, x2, x1 +ADD x2, x2, x1 +ADD x3, x4, x1 +ADD x4, x4, x4 +ADD x4, x0, x5 +ADD x1, x0, x5 +ADD x1, x2, x3 +ADD x5, x0, x2 +ADD x4, x0, x1 +ADD x2, x1, x5 +ADD x2, x1, x2 +ADD x4, x0, x4 +ADD x3, x1, x2 +ADD x3, x1, x2 +ADD x4, x1, x4 +ADD x4, x4, x2 +ADD x1, x1, x5 +ADD x2, x5, x2 +ADD x5, x0, x3 +ADD x1, x0, x1 +ADD x1, x1, x4 +ADD x3, x3, x5 +ADD x5, x1, x3 +ADD x1, x4, x4 +ADD x3, x3, x5 +ADD x2, x3, x4 +ADD x4, x3, x2 +ADD x4, x5, x4 +ADD x5, x2, x3 +ADD x5, x4, x1 +ADD x1, x1, x3 +ADD x5, x3, x1 +ADD x1, x1, x4 +ADD x4, x5, x4 +ADD x5, x5, x4 +ADD x3, x1, x2 +ADD x5, x3, x2 +ADD x3, x4, x1 +ADD x4, x1, x3 +ADD x2, x1, x3 +ADD x1, x2, x4 +ADD x1, x4, x4 +ADD x2, x2, x4 +ADD x1, x1, x2 +ADD x4, x1, x1 +ADD x1, x3, x1 +ADD x2, x4, x5 +ADD x2, x1, x2 +ADD x2, x0, x5 +ADD x3, x2, x5 +ADD x4, x5, x1 +ADD x5, x1, x3 +ADD x4, x4, x2 +ADD x3, x1, x4 +ADD x3, x3, x5 +ADD x2, x3, x1 +ADD x5, x0, x5 +ADD x5, x5, x2 +ADD x2, x2, x5 +ADD x1, x0, x1 +ADD x3, x2, x4 +ADD x3, x5, x4 +ADD x2, x5, x4 +ADD x1, x4, x5 +ADD x5, x0, x2 +ADD x4, x4, x2 +ADD x5, x2, x1 +ADD x4, x3, x2 +ADD x5, x3, x1 +ADD x5, x2, x2 +ADD x5, x0, x4 +ADD x4, x2, x5 +ADD x2, x3, x3 +ADD x2, x4, x3 +ADD x4, x4, x2 +ADD x4, x0, x4 +ADD x3, x4, x1 +ADD x3, x1, x1 +ADD x2, x2, x1 +ADD x5, x5, x2 +ADD x4, x0, x1 +ADD x4, x5, x1 +ADD x1, x2, x1 +ADD x3, x1, x4 +ADD x4, x1, x1 +ADD x1, x4, x3 +ADD x4, x2, x5 +ADD x4, x5, x3 +ADD x2, x1, x3 +ADD x3, x5, x3 +ADD x1, x4, x2 +ADD x4, x2, x5 +ADD x3, x5, x3 +ADD x4, x2, x3 +ADD x3, x0, x4 +ADD x3, x3, x2 +ADD x3, x5, x2 +ADD x4, x1, x1 +ADD x4, x3, x5 +ADD x5, x5, x4 +ADD x3, x3, x2 +ADD x3, x0, x4 +ADD x1, x1, x4 +ADD x3, x3, x1 +ADD x2, x5, x3 +ADD x1, x1, x3 +ADD x4, x0, x1 +ADD x5, x1, x1 +ADD x2, x0, x4 +ADD x4, x4, x5 +ADD x2, x4, x2 +ADD x4, x3, x4 +ADD x4, x3, x2 +ADD x1, x4, x3 +ADD x3, x5, x3 +ADD x5, x5, x2 +ADD x1, x2, x1 +ADD x5, x0, x2 +ADD x5, x3, x2 +ADD x5, x1, x4 +ADD x4, x4, x1 +ADD x4, x4, x4 +ADD x3, x3, x5 +ADD x4, x3, x3 +ADD x3, x4, x5 +ADD x3, x3, x2 +ADD x4, x3, x1 +ADD x4, x4, x4 +ADD x3, x3, x2 +ADD x2, x3, x2 +ADD x4, x2, x3 +ADD x2, x4, x1 +ADD x1, x4, x1 +ADD x3, x2, x1 +ADD x2, x3, x4 +ADD x2, x3, x2 +ADD x5, x0, x3 +ADD x2, x5, x3 +ADD x4, x1, x5 +ADD x1, x4, x4 +ADD x3, x3, x5 +ADD x1, x0, x1 +ADD x5, x1, x4 +ADD x5, x5, x1 +ADD x3, x5, x3 +ADD x2, x5, x2 +ADD x4, x4, x3 +ADD x4, x3, x3 +ADD x1, x1, x2 +ADD x5, x3, x4 +ADD x1, x2, x1 +ADD x4, x1, x1 +ADD x1, x4, x2 +ADD x3, x4, x4 +ADD x1, x4, x5 +ADD x1, x4, x4 +ADD x3, x3, x5 +ADD x2, x0, x1 +ADD x3, x4, x5 +ADD x1, x3, x3 +ADD x4, x2, x2 +ADD x3, x5, x5 +ADD x1, x4, x3 +ADD x5, x1, x3 +ADD x4, x0, x5 +ADD x1, x2, x4 +ADD x2, x3, x5 +ADD x4, x0, x1 +ADD x3, x0, x3 +ADD x3, x0, x3 +ADD x5, x4, x2 +ADD x5, x2, x5 +ADD x1, x1, x4 +ADD x3, x2, x2 +ADD x4, x4, x5 +ADD x1, x2, x5 +ADD x4, x4, x2 +ADD x3, x4, x2 +ADD x2, x4, x2 +ADD x5, x3, x2 +ADD x3, x2, x2 +ADD x2, x4, x2 +ADD x3, x2, x2 +ADD x3, x0, x3 +ADD x5, x0, x1 +ADD x2, x2, x1 +ADD x5, x1, x5 +ADD x4, x3, x1 +ADD x5, x0, x1 +ADD x3, x2, x2 +ADD x3, x5, x4 +ADD x3, x0, x1 +ADD x3, x5, x3 +ADD x5, x0, x2 +ADD x1, x2, x5 +ADD x5, x3, x3 +ADD x5, x2, x3 +ADD x4, x3, x1 +ADD x1, x1, x5 +ADD x4, x5, x4 +ADD x3, x1, x1 +ADD x4, x1, x2 +ADD x4, x2, x5 +ADD x4, x4, x2 +ADD x4, x2, x4 +ADD x2, x5, x1 +ADD x2, x1, x2 +ADD x2, x2, x2 +ADD x2, x4, x1 +ADD x2, x5, x4 +ADD x5, x4, x2 +ADD x5, x5, x2 +ADD x4, x5, x1 +ADD x2, x0, x4 +ADD x2, x4, x4 +ADD x4, x4, x5 +ADD x5, x1, x1 +ADD x2, x0, x1 +ADD x4, x3, x3 +ADD x3, x5, x4 +ADD x2, x1, x5 +ADD x5, x0, x1 +ADD x2, x5, x4 +ADD x5, x5, x2 +ADD x2, x0, x5 +ADD x3, x5, x3 +ADD x2, x4, x3 +ADD x5, x3, x2 +ADD x3, x2, x4 +ADD x3, x1, x4 +ADD x4, x2, x5 +ADD x5, x4, x4 +ADD x2, x5, x5 +ADD x3, x3, x2 +ADD x5, x4, x2 +ADD x4, x2, x3 +ADD x1, x3, x5 +ADD x1, x2, x4 +ADD x1, x1, x5 +ADD x2, x0, x2 +ADD x5, x5, x3 +ADD x1, x0, x1 +ADD x4, x2, x2 +ADD x3, x5, x3 +ADD x1, x4, x4 +ADD x5, x1, x1 +ADD x4, x2, x2 +ADD x2, x2, x2 +ADD x5, x5, x2 +ADD x1, x4, x2 +ADD x1, x3, x5 +ADD x4, x4, x1 +ADD x2, x2, x5 +ADD x3, x2, x2 +ADD x5, x3, x4 +ADD x4, x2, x1 +ADD x3, x0, x5 +ADD x4, x4, x4 +ADD x2, x4, x4 +ADD x2, x4, x1 +ADD x4, x2, x1 +ADD x3, x2, x1 +ADD x5, x0, x1 +ADD x4, x1, x1 +ADD x3, x3, x1 +ADD x5, x0, x4 +ADD x4, x0, x2 +ADD x4, x0, x5 +ADD x4, x4, x3 +ADD x4, x4, x1 +ADD x2, x4, x2 +ADD x4, x0, x5 +ADD x2, x2, x3 +ADD x1, x5, x1 +ADD x2, x0, x3 +ADD x1, x4, x2 +ADD x2, x0, x3 +ADD x1, x4, x1 +ADD x4, x1, x3 +ADD x4, x5, x4 +ADD x4, x0, x3 +ADD x4, x3, x5 +ADD x2, x4, x1 +ADD x5, x5, x4 +ADD x2, x1, x1 +ADD x5, x0, x4 +ADD x5, x5, x1 +ADD x3, x4, x3 +ADD x3, x3, x5 +ADD x2, x4, x3 +ADD x3, x5, x4 +ADD x2, x4, x1 +ADD x3, x3, x1 +ADD x5, x4, x2 +ADD x1, x4, x5 +ADD x1, x4, x3 +ADD x3, x1, x3 +ADD x1, x3, x4 +ADD x3, x5, x4 +ADD x5, x0, x4 +ADD x5, x3, x3 +ADD x4, x1, x1 +ADD x3, x4, x4 +ADD x2, x3, x5 +ADD x3, x3, x2 +ADD x2, x2, x2 +ADD x5, x1, x5 +ADD x5, x3, x2 +ADD x3, x4, x2 +ADD x5, x1, x3 +ADD x1, x4, x5 +ADD x2, x3, x2 +ADD x1, x4, x2 +ADD x4, x1, x3 +ADD x3, x4, x2 +ADD x1, x2, x1 +ADD x2, x1, x5 +ADD x5, x0, x3 +ADD x4, x5, x4 +ADD x1, x5, x4 +ADD x2, x0, x3 +ADD x4, x4, x5 +ADD x4, x4, x4 +ADD x1, x1, x1 +ADD x5, x4, x1 +ADD x1, x5, x5 +ADD x1, x0, x1 +ADD x4, x0, x5 +ADD x5, x4, x5 +ADD x2, x2, x3 +ADD x2, x4, x2 +ADD x4, x1, x3 +ADD x3, x1, x5 +ADD x4, x0, x2 +ADD x1, x1, x5 +ADD x2, x4, x4 +ADD x3, x0, x5 +ADD x2, x0, x2 +ADD x2, x3, x2 +ADD x5, x4, x1 +ADD x4, x1, x2 +ADD x2, x5, x4 +ADD x1, x5, x2 +ADD x3, x3, x3 +ADD x5, x1, x3 +ADD x4, x0, x2 +ADD x5, x4, x1 +ADD x2, x5, x4 +ADD x2, x2, x5 +ADD x3, x5, x1 +ADD x5, x2, x4 +ADD x4, x2, x4 +ADD x5, x5, x5 +ADD x3, x5, x1 +ADD x4, x4, x5 +ADD x4, x3, x2 +ADD x4, x0, x5 +ADD x2, x4, x4 +ADD x2, x1, x2 +ADD x4, x4, x4 +ADD x5, x4, x2 +ADD x1, x1, x4 +ADD x2, x0, x5 +ADD x5, x4, x5 +ADD x3, x4, x4 +ADD x1, x5, x5 +ADD x1, x2, x2 +ADD x5, x3, x2 +ADD x2, x0, x2 +ADD x5, x3, x1 +ADD x4, x5, x3 +ADD x1, x5, x3 +ADD x5, x3, x3 +ADD x4, x1, x2 +ADD x3, x0, x4 +ADD x2, x4, x3 +ADD x3, x4, x3 +ADD x2, x2, x2 +ADD x4, x4, x4 +ADD x4, x0, x2 +ADD x5, x2, x2 +ADD x3, x4, x4 +ADD x5, x4, x2 +ADD x1, x2, x2 +ADD x5, x1, x4 +ADD x3, x1, x1 +ADD x3, x4, x1 +ADD x2, x0, x4 +ADD x1, x0, x5 +ADD x3, x2, x5 +ADD x1, x1, x2 +ADD x1, x3, x2 +ADD x2, x1, x5 +ADD x2, x4, x5 +ADD x1, x0, x3 +ADD x5, x4, x4 +ADD x1, x4, x4 +ADD x1, x1, x4 +ADD x4, x2, x3 +ADD x2, x0, x3 +ADD x2, x0, x5 +ADD x4, x4, x2 +ADD x4, x0, x3 +ADD x5, x5, x3 +ADD x1, x1, x3 +ADD x2, x5, x3 +ADD x3, x2, x1 +ADD x4, x3, x1 +ADD x5, x0, x3 +ADD x5, x3, x5 +ADD x3, x1, x1 +ADD x2, x3, x3 +ADD x5, x3, x3 +ADD x4, x1, x5 +ADD x2, x1, x1 +ADD x1, x2, x1 +ADD x5, x2, x3 +ADD x2, x2, x4 +ADD x4, x1, x3 +ADD x4, x1, x3 +ADD x5, x3, x3 +ADD x4, x0, x5 +ADD x5, x0, x1 +ADD x2, x5, x4 +ADD x4, x5, x1 +ADD x5, x5, x3 +ADD x5, x2, x3 +ADD x1, x4, x3 +ADD x3, x0, x1 +ADD x2, x3, x2 +ADD x4, x5, x5 +ADD x4, x4, x2 +ADD x1, x0, x1 +ADD x3, x2, x2 +ADD x1, x4, x3 +ADD x3, x4, x5 +ADD x2, x1, x1 +ADD x4, x1, x2 +ADD x4, x5, x2 +ADD x1, x4, x4 +ADD x1, x0, x3 +ADD x4, x1, x3 +ADD x5, x3, x5 +ADD x1, x1, x4 +ADD x3, x4, x2 +ADD x4, x4, x3 +ADD x3, x5, x3 +ADD x2, x1, x2 +ADD x3, x2, x1 +ADD x2, x4, x3 +ADD x5, x0, x4 +ADD x5, x1, x4 +ADD x1, x4, x2 +ADD x4, x3, x4 +ADD x5, x0, x2 +ADD x2, x0, x4 +ADD x5, x5, x5 +ADD x2, x4, x3 +ADD x5, x3, x1 +ADD x1, x5, x3 +ADD x4, x4, x3 +ADD x3, x5, x5 +ADD x3, x0, x1 +ADD x4, x5, x4 +ADD x4, x2, x4 +ADD x3, x5, x4 +ADD x4, x1, x4 +ADD x5, x5, x5 +ADD x3, x3, x5 +ADD x2, x3, x5 +ADD x4, x0, x4 +ADD x2, x2, x1 +ADD x1, x1, x4 +ADD x4, x1, x2 +ADD x5, x0, x2 +ADD x1, x1, x2 +ADD x2, x5, x4 +ADD x3, x3, x4 +ADD x2, x1, x4 +ADD x4, x5, x1 +ADD x3, x5, x3 +ADD x3, x0, x5 +ADD x1, x3, x1 +ADD x3, x1, x4 +ADD x4, x3, x1 +ADD x3, x0, x1 +ADD x1, x2, x3 +ADD x1, x0, x5 +ADD x4, x4, x2 +ADD x1, x4, x2 +ADD x1, x0, x1 +ADD x4, x1, x1 +ADD x4, x0, x1 +ADD x5, x4, x2 +ADD x4, x1, x3 +ADD x1, x0, x5 +ADD x3, x0, x4 +ADD x5, x4, x5 +ADD x5, x2, x2 +ADD x4, x1, x5 +ADD x3, x5, x3 +ADD x1, x0, x1 +ADD x2, x2, x2 +ADD x4, x0, x4 +ADD x2, x2, x3 +ADD x3, x1, x3 +ADD x5, x5, x1 +ADD x3, x1, x3 +ADD x5, x5, x1 +ADD x1, x2, x4 +ADD x3, x3, x5 +ADD x2, x5, x3 +ADD x5, x0, x4 +ADD x1, x1, x3 +ADD x3, x5, x1 +ADD x2, x0, x3 +ADD x5, x2, x3 +ADD x2, x1, x4 +ADD x1, x3, x3 +ADD x5, x0, x1 +ADD x4, x2, x2 +ADD x2, x4, x5 +ADD x2, x5, x5 +ADD x5, x4, x4 +ADD x1, x2, x3 +ADD x2, x3, x3 +ADD x5, x1, x4 +ADD x5, x5, x2 +ADD x2, x3, x4 +ADD x4, x5, x4 +ADD x3, x5, x2 +ADD x5, x5, x2 +ADD x1, x2, x2 +ADD x4, x2, x2 +ADD x3, x4, x4 +ADD x1, x3, x4 +ADD x3, x4, x3 +ADD x4, x5, x3 +ADD x5, x3, x5 +ADD x4, x3, x3 +ADD x5, x0, x4 +ADD x1, x2, x1 +ADD x5, x5, x4 +ADD x5, x4, x4 +ADD x5, x4, x4 +ADD x5, x4, x1 +ADD x4, x1, x3 +ADD x2, x1, x1 +ADD x4, x5, x2 +ADD x4, x3, x2 +ADD x5, x3, x3 +ADD x5, x0, x3 +ADD x5, x3, x5 +ADD x5, x2, x2 +ADD x3, x1, x1 +ADD x4, x0, x1 +ADD x5, x0, x5 +ADD x5, x1, x4 +ADD x1, x4, x3 +ADD x4, x2, x2 +ADD x1, x0, x3 +ADD x3, x4, x1 +ADD x2, x4, x3 +ADD x4, x5, x4 +ADD x1, x5, x2 +ADD x4, x2, x4 +ADD x4, x3, x2 +ADD x3, x3, x2 +ADD x3, x1, x4 +ADD x3, x2, x4 +ADD x2, x1, x4 +ADD x2, x1, x4 +ADD x5, x4, x5 +ADD x2, x5, x3 +ADD x2, x5, x3 +ADD x1, x2, x1 +ADD x3, x2, x3 +ADD x3, x0, x2 +ADD x2, x1, x5 +ADD x5, x1, x1 +ADD x1, x5, x1 +ADD x4, x5, x1 +ADD x2, x3, x2 +ADD x1, x0, x2 +ADD x3, x4, x1 +ADD x1, x4, x5 +ADD x4, x5, x3 +ADD x3, x4, x4 +ADD x4, x5, x2 +ADD x1, x1, x2 +ADD x3, x5, x5 +ADD x3, x5, x1 +ADD x1, x2, x4 +ADD x4, x2, x2 +ADD x2, x1, x1 +ADD x3, x3, x1 +ADD x2, x0, x3 +ADD x5, x1, x5 +ADD x3, x5, x4 +ADD x3, x4, x3 +ADD x2, x4, x5 +ADD x5, x1, x5 +ADD x2, x2, x4 +ADD x5, x0, x4 +ADD x5, x3, x3 +ADD x4, x1, x3 +ADD x4, x4, x1 +ADD x5, x0, x1 +ADD x1, x1, x1 +ADD x1, x2, x2 +ADD x3, x1, x2 +ADD x5, x5, x5 +ADD x4, x3, x2 +ADD x5, x4, x2 +ADD x4, x3, x1 +ADD x5, x1, x1 +ADD x3, x2, x3 +ADD x4, x2, x5 +ADD x5, x2, x3 +ADD x3, x3, x5 +ADD x4, x5, x3 +ADD x2, x5, x1 +ADD x4, x2, x4 +ADD x2, x1, x4 +ADD x1, x4, x2 +ADD x2, x4, x5 +ADD x1, x5, x4 +ADD x2, x1, x4 +ADD x1, x0, x5 +ADD x5, x5, x1 +ADD x2, x1, x5 +ADD x1, x2, x1 +ADD x3, x3, x2 +ADD x5, x4, x2 +ADD x1, x4, x3 +sw x1, 0(x8) +sw x2, 4(x8) +sw x3, 8(x8) +sw x4, 12(x8) +sw x5, 16(x8) +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN + + +signature_x8_0: + .fill 0*(XLEN/32),4,0xdeadbeef + + +signature_x8_1: + .fill 19*(XLEN/32),4,0xdeadbeef + + +signature_x1_0: + .fill 256*(XLEN/32),4,0xdeadbeef + + +signature_x1_1: + .fill 256*(XLEN/32),4,0xdeadbeef + + +signature_x1_2: + .fill 148*(XLEN/32),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine + +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef + +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*(XLEN/32),4,0xdeadbeef + +#endif + +RVMODEL_DATA_END +// ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/PIPELINE.S +// David_Harris@hmc.edu diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/PIPELINE.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/PIPELINE.S new file mode 100644 index 000000000..8ecc6a5a8 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/PIPELINE.S @@ -0,0 +1,1082 @@ +/////////////////////////////////////////// +// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/PIPELINE.S +// David_Harris@hmc.edu +// Created 2021-11-01 13:22:54.989066// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "model_test.h" +#include "arch_test.h" + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +RVTEST_SIGBASE( x8,signature_x8_1) +ADD x2, x3, x1 +ADD x3, x1, x3 +ADD x3, x1, x4 +ADD x1, x0, x4 +ADD x4, x1, x3 +ADD x5, x2, x4 +ADD x4, x2, x1 +ADD x4, x2, x2 +ADD x2, x2, x3 +ADD x4, x4, x3 +ADD x2, x4, x2 +ADD x1, x5, x4 +ADD x3, x2, x4 +ADD x4, x3, x1 +ADD x3, x1, x3 +ADD x4, x4, x2 +ADD x3, x0, x5 +ADD x3, x3, x1 +ADD x1, x4, x2 +ADD x5, x4, x4 +ADD x2, x3, x3 +ADD x1, x4, x2 +ADD x2, x1, x1 +ADD x1, x5, x2 +ADD x3, x2, x3 +ADD x1, x3, x5 +ADD x2, x3, x4 +ADD x5, x0, x5 +ADD x2, x5, x3 +ADD x2, x2, x2 +ADD x3, x1, x1 +ADD x3, x1, x3 +ADD x1, x3, x1 +ADD x1, x3, x4 +ADD x2, x5, x5 +ADD x4, x1, x3 +ADD x5, x1, x2 +ADD x2, x3, x3 +ADD x1, x3, x1 +ADD x2, x4, x2 +ADD x5, x5, x2 +ADD x1, x4, x5 +ADD x1, x2, x5 +ADD x5, x5, x3 +ADD x1, x4, x3 +ADD x3, x2, x1 +ADD x3, x2, x1 +ADD x1, x2, x1 +ADD x2, x0, x4 +ADD x3, x4, x4 +ADD x4, x1, x5 +ADD x1, x5, x1 +ADD x4, x1, x4 +ADD x5, x5, x2 +ADD x4, x0, x1 +ADD x4, x2, x2 +ADD x4, x5, x3 +ADD x5, x4, x3 +ADD x4, x5, x1 +ADD x2, x4, x1 +ADD x5, x3, x2 +ADD x2, x1, x1 +ADD x3, x2, x3 +ADD x5, x1, x2 +ADD x4, x2, x1 +ADD x2, x4, x4 +ADD x4, x1, x4 +ADD x5, x4, x4 +ADD x5, x0, x5 +ADD x4, x1, x5 +ADD x1, x1, x5 +ADD x3, x1, x2 +ADD x2, x2, x1 +ADD x3, x4, x4 +ADD x1, x2, x2 +ADD x5, x5, x4 +ADD x2, x3, x1 +ADD x1, x1, x3 +ADD x3, x3, x3 +ADD x3, x2, x1 +ADD x2, x1, x3 +ADD x4, x1, x2 +ADD x2, x4, x3 +ADD x5, x3, x1 +ADD x1, x4, x4 +ADD x5, x5, x2 +ADD x1, x5, x1 +ADD x3, x5, x5 +ADD x3, x1, x1 +ADD x3, x1, x4 +ADD x2, x4, x5 +ADD x3, x3, x2 +ADD x1, x2, x3 +ADD x5, x3, x3 +ADD x4, x0, x4 +ADD x3, x2, x5 +ADD x1, x1, x3 +ADD x4, x5, x1 +ADD x4, x0, x1 +ADD x4, x2, x1 +ADD x5, x4, x1 +ADD x5, x3, x4 +ADD x2, x1, x2 +ADD x5, x0, x5 +ADD x4, x2, x3 +ADD x5, x3, x2 +ADD x1, x2, x2 +ADD x5, x1, x1 +ADD x1, x4, x2 +ADD x5, x5, x4 +ADD x5, x2, x3 +ADD x4, x1, x1 +ADD x2, x4, x3 +ADD x4, x2, x1 +ADD x4, x0, x1 +ADD x4, x2, x3 +ADD x2, x2, x3 +ADD x3, x5, x3 +ADD x4, x1, x1 +ADD x1, x3, x5 +ADD x4, x2, x1 +ADD x1, x0, x2 +ADD x2, x1, x3 +ADD x3, x1, x4 +ADD x4, x0, x1 +ADD x2, x5, x4 +ADD x1, x5, x4 +ADD x5, x0, x2 +ADD x1, x0, x3 +ADD x3, x1, x4 +ADD x5, x4, x3 +ADD x5, x5, x4 +ADD x2, x1, x2 +ADD x1, x0, x2 +ADD x1, x4, x5 +ADD x4, x3, x4 +ADD x5, x5, x5 +ADD x2, x5, x5 +ADD x5, x4, x3 +ADD x5, x5, x4 +ADD x5, x3, x5 +ADD x5, x3, x3 +ADD x3, x5, x1 +ADD x3, x5, x5 +ADD x5, x3, x1 +ADD x4, x2, x1 +ADD x1, x5, x1 +ADD x5, x4, x1 +ADD x1, x4, x1 +ADD x1, x2, x4 +ADD x3, x3, x2 +ADD x4, x2, x2 +ADD x3, x3, x3 +ADD x5, x4, x5 +ADD x1, x0, x3 +ADD x3, x3, x4 +ADD x2, x2, x5 +ADD x4, x4, x4 +ADD x1, x3, x1 +ADD x3, x4, x1 +ADD x1, x2, x3 +ADD x2, x5, x3 +ADD x5, x3, x1 +ADD x5, x2, x3 +ADD x1, x0, x3 +ADD x3, x4, x2 +ADD x4, x5, x3 +ADD x2, x3, x2 +ADD x1, x1, x1 +ADD x5, x3, x4 +ADD x1, x2, x1 +ADD x2, x2, x2 +ADD x5, x0, x4 +ADD x2, x2, x1 +ADD x4, x0, x3 +ADD x4, x0, x3 +ADD x2, x2, x3 +ADD x2, x5, x5 +ADD x4, x4, x1 +ADD x2, x0, x5 +ADD x1, x4, x2 +ADD x5, x1, x2 +ADD x4, x4, x4 +ADD x2, x3, x3 +ADD x3, x2, x3 +ADD x1, x1, x4 +ADD x2, x5, x1 +ADD x1, x4, x2 +ADD x5, x4, x2 +ADD x2, x0, x2 +ADD x1, x3, x4 +ADD x5, x2, x3 +ADD x1, x1, x5 +ADD x1, x2, x3 +ADD x4, x2, x1 +ADD x3, x2, x5 +ADD x2, x1, x5 +ADD x3, x4, x1 +ADD x3, x4, x2 +ADD x4, x3, x3 +ADD x3, x3, x4 +ADD x3, x2, x2 +ADD x1, x2, x4 +ADD x3, x2, x3 +ADD x2, x3, x2 +ADD x5, x4, x4 +ADD x2, x5, x5 +ADD x1, x2, x2 +ADD x1, x3, x5 +ADD x5, x3, x3 +ADD x5, x3, x1 +ADD x4, x3, x5 +ADD x4, x4, x4 +ADD x2, x0, x3 +ADD x5, x2, x1 +ADD x4, x1, x5 +ADD x3, x5, x2 +ADD x4, x3, x3 +ADD x3, x4, x2 +ADD x3, x3, x2 +ADD x3, x2, x1 +ADD x1, x5, x2 +ADD x2, x4, x4 +ADD x5, x5, x5 +ADD x5, x1, x4 +ADD x5, x2, x4 +ADD x4, x0, x5 +ADD x2, x2, x3 +ADD x4, x3, x3 +ADD x2, x3, x2 +ADD x4, x3, x1 +ADD x4, x4, x3 +ADD x2, x2, x3 +ADD x2, x1, x3 +ADD x5, x2, x2 +ADD x2, x0, x1 +ADD x3, x4, x3 +ADD x5, x0, x3 +ADD x3, x0, x4 +ADD x5, x5, x5 +ADD x5, x0, x5 +ADD x4, x0, x3 +ADD x2, x2, x5 +ADD x1, x3, x4 +ADD x2, x4, x3 +ADD x4, x0, x2 +ADD x3, x0, x3 +ADD x1, x4, x1 +ADD x5, x1, x3 +ADD x1, x1, x1 +ADD x2, x5, x3 +ADD x4, x4, x1 +ADD x1, x2, x1 +ADD x2, x2, x2 +ADD x2, x3, x4 +ADD x3, x0, x5 +ADD x5, x5, x2 +ADD x3, x4, x3 +ADD x4, x4, x2 +ADD x5, x4, x1 +ADD x1, x2, x4 +ADD x3, x0, x3 +ADD x1, x4, x3 +ADD x1, x2, x5 +ADD x2, x3, x4 +ADD x2, x1, x2 +ADD x1, x0, x5 +ADD x5, x3, x5 +ADD x2, x3, x2 +ADD x3, x2, x2 +ADD x2, x3, x4 +ADD x2, x2, x4 +ADD x5, x5, x2 +ADD x3, x4, x4 +ADD x2, x2, x4 +ADD x5, x5, x5 +ADD x5, x0, x2 +ADD x3, x5, x5 +ADD x2, x2, x4 +ADD x5, x1, x3 +ADD x1, x0, x3 +ADD x5, x5, x1 +ADD x1, x5, x1 +ADD x4, x4, x3 +ADD x5, x5, x1 +ADD x3, x0, x4 +ADD x1, x2, x1 +ADD x5, x5, x1 +ADD x1, x5, x5 +ADD x5, x1, x5 +ADD x1, x2, x1 +ADD x5, x0, x2 +ADD x5, x1, x4 +ADD x1, x3, x2 +ADD x2, x0, x2 +ADD x1, x5, x4 +ADD x2, x1, x1 +ADD x4, x5, x4 +ADD x5, x4, x2 +ADD x2, x4, x4 +ADD x2, x5, x5 +ADD x5, x2, x4 +ADD x5, x5, x4 +ADD x2, x2, x5 +ADD x5, x2, x5 +ADD x2, x2, x3 +ADD x4, x2, x3 +ADD x2, x5, x3 +ADD x2, x2, x3 +ADD x5, x1, x4 +ADD x4, x2, x2 +ADD x5, x1, x3 +ADD x5, x3, x1 +ADD x2, x3, x1 +ADD x3, x4, x3 +ADD x2, x3, x4 +ADD x1, x4, x2 +ADD x4, x3, x3 +ADD x4, x0, x3 +ADD x2, x0, x1 +ADD x4, x1, x3 +ADD x4, x4, x3 +ADD x3, x5, x1 +ADD x2, x4, x2 +ADD x4, x0, x1 +ADD x1, x2, x5 +ADD x2, x3, x5 +ADD x5, x1, x1 +ADD x3, x2, x1 +ADD x5, x5, x4 +ADD x1, x2, x4 +ADD x2, x3, x4 +ADD x5, x5, x1 +ADD x5, x4, x2 +ADD x2, x2, x3 +ADD x1, x2, x3 +ADD x1, x0, x4 +ADD x4, x2, x3 +ADD x2, x0, x5 +ADD x3, x3, x2 +ADD x1, x0, x2 +ADD x5, x2, x4 +ADD x3, x2, x5 +ADD x4, x1, x1 +ADD x2, x5, x1 +ADD x2, x2, x4 +ADD x3, x5, x3 +ADD x5, x4, x1 +ADD x1, x5, x4 +ADD x1, x3, x1 +ADD x4, x5, x2 +ADD x1, x3, x5 +ADD x3, x3, x3 +ADD x4, x0, x5 +ADD x5, x4, x2 +ADD x5, x1, x4 +ADD x5, x1, x5 +ADD x3, x5, x2 +ADD x5, x2, x1 +ADD x4, x5, x3 +ADD x5, x0, x2 +ADD x3, x1, x4 +ADD x4, x0, x4 +ADD x1, x5, x2 +ADD x3, x3, x2 +ADD x5, x4, x3 +ADD x3, x5, x1 +ADD x4, x5, x1 +ADD x2, x2, x3 +ADD x5, x4, x5 +ADD x2, x3, x2 +ADD x4, x1, x2 +ADD x2, x0, x1 +ADD x1, x3, x4 +ADD x3, x4, x3 +ADD x3, x4, x2 +ADD x5, x3, x1 +ADD x3, x0, x4 +ADD x1, x4, x5 +ADD x2, x2, x4 +ADD x1, x2, x1 +ADD x4, x5, x5 +ADD x4, x3, x2 +ADD x2, x4, x4 +ADD x4, x0, x5 +ADD x2, x3, x3 +ADD x3, x4, x5 +ADD x4, x4, x2 +ADD x3, x0, x2 +ADD x4, x4, x3 +ADD x1, x5, x4 +ADD x5, x2, x4 +ADD x1, x3, x5 +ADD x4, x1, x4 +ADD x4, x3, x2 +ADD x5, x0, x3 +ADD x5, x4, x2 +ADD x2, x5, x1 +ADD x5, x4, x5 +ADD x3, x4, x4 +ADD x3, x0, x4 +ADD x1, x3, x1 +ADD x1, x1, x4 +ADD x5, x3, x4 +ADD x1, x0, x3 +ADD x1, x3, x5 +ADD x2, x0, x3 +ADD x2, x1, x2 +ADD x1, x4, x1 +ADD x2, x3, x3 +ADD x1, x0, x5 +ADD x4, x5, x2 +ADD x3, x0, x4 +ADD x1, x4, x2 +ADD x5, x5, x3 +ADD x5, x4, x5 +ADD x3, x4, x5 +ADD x3, x1, x2 +ADD x4, x0, x3 +ADD x5, x4, x3 +ADD x4, x0, x3 +ADD x4, x1, x1 +ADD x5, x4, x3 +ADD x1, x1, x1 +ADD x3, x0, x2 +ADD x3, x5, x1 +ADD x1, x3, x1 +ADD x3, x1, x3 +ADD x1, x1, x5 +ADD x3, x2, x3 +ADD x3, x0, x4 +ADD x2, x2, x1 +ADD x2, x2, x2 +ADD x5, x3, x3 +ADD x5, x1, x2 +ADD x3, x4, x1 +ADD x2, x0, x3 +ADD x2, x4, x5 +ADD x4, x4, x1 +ADD x3, x2, x5 +ADD x5, x5, x5 +ADD x3, x3, x1 +ADD x2, x3, x3 +ADD x4, x2, x4 +ADD x2, x5, x2 +ADD x2, x3, x2 +ADD x4, x0, x3 +ADD x5, x0, x5 +ADD x2, x2, x2 +ADD x3, x3, x4 +ADD x4, x2, x3 +ADD x4, x3, x2 +ADD x3, x3, x5 +ADD x2, x0, x1 +ADD x1, x2, x2 +ADD x1, x2, x5 +ADD x5, x5, x4 +ADD x4, x0, x4 +ADD x2, x1, x1 +ADD x2, x5, x5 +ADD x3, x2, x1 +ADD x3, x5, x1 +ADD x4, x2, x2 +ADD x5, x5, x4 +ADD x4, x5, x4 +ADD x1, x0, x3 +ADD x1, x3, x4 +ADD x1, x4, x1 +ADD x2, x0, x4 +ADD x3, x4, x5 +ADD x1, x0, x5 +ADD x2, x1, x5 +ADD x2, x1, x4 +ADD x5, x4, x1 +ADD x3, x3, x4 +ADD x5, x2, x5 +ADD x1, x1, x5 +ADD x3, x3, x4 +ADD x1, x1, x1 +ADD x2, x3, x4 +ADD x5, x4, x2 +ADD x3, x1, x2 +ADD x1, x3, x5 +ADD x1, x3, x2 +ADD x4, x3, x2 +ADD x4, x0, x3 +ADD x3, x2, x4 +ADD x1, x5, x3 +ADD x2, x3, x3 +ADD x4, x2, x1 +ADD x4, x1, x5 +ADD x3, x5, x4 +ADD x3, x0, x2 +ADD x1, x1, x3 +ADD x5, x1, x2 +ADD x3, x5, x3 +ADD x4, x1, x5 +ADD x5, x1, x4 +ADD x4, x0, x3 +ADD x5, x1, x5 +ADD x3, x5, x3 +ADD x4, x1, x3 +ADD x4, x2, x4 +ADD x4, x1, x5 +ADD x4, x2, x4 +ADD x4, x0, x3 +ADD x3, x5, x1 +ADD x1, x2, x4 +ADD x3, x5, x5 +ADD x3, x4, x4 +ADD x4, x0, x3 +ADD x4, x4, x1 +ADD x3, x5, x1 +ADD x5, x4, x4 +ADD x3, x1, x1 +ADD x2, x4, x5 +ADD x1, x4, x4 +ADD x3, x2, x3 +ADD x5, x3, x2 +ADD x5, x4, x5 +ADD x3, x2, x4 +ADD x2, x2, x2 +ADD x2, x3, x2 +ADD x5, x2, x2 +ADD x4, x1, x1 +ADD x5, x1, x5 +ADD x4, x3, x2 +ADD x1, x4, x1 +ADD x1, x1, x1 +ADD x3, x0, x4 +ADD x3, x3, x4 +ADD x3, x5, x5 +ADD x4, x5, x3 +ADD x2, x0, x5 +ADD x4, x4, x5 +ADD x2, x2, x5 +ADD x1, x0, x2 +ADD x5, x0, x2 +ADD x5, x5, x4 +ADD x5, x5, x1 +ADD x5, x0, x2 +ADD x4, x0, x4 +ADD x3, x0, x1 +ADD x2, x4, x3 +ADD x5, x3, x2 +ADD x4, x4, x5 +ADD x3, x0, x1 +ADD x5, x3, x2 +ADD x4, x0, x1 +ADD x5, x3, x3 +ADD x1, x1, x5 +ADD x4, x4, x2 +ADD x3, x0, x5 +ADD x2, x3, x3 +ADD x5, x3, x4 +ADD x5, x4, x5 +ADD x3, x2, x1 +ADD x3, x0, x5 +ADD x1, x4, x3 +ADD x3, x2, x2 +ADD x3, x1, x4 +ADD x5, x2, x3 +ADD x4, x1, x4 +ADD x4, x3, x4 +ADD x1, x1, x4 +ADD x1, x0, x4 +ADD x5, x0, x2 +ADD x1, x5, x1 +ADD x1, x1, x5 +ADD x1, x3, x2 +ADD x2, x2, x5 +ADD x1, x0, x1 +ADD x1, x4, x1 +ADD x1, x4, x1 +ADD x5, x2, x4 +ADD x5, x2, x3 +ADD x2, x2, x3 +ADD x2, x1, x3 +ADD x4, x1, x5 +ADD x5, x3, x1 +ADD x3, x4, x1 +ADD x1, x0, x4 +ADD x1, x1, x3 +ADD x4, x0, x5 +ADD x2, x3, x4 +ADD x3, x5, x1 +ADD x5, x3, x3 +ADD x1, x5, x1 +ADD x4, x3, x2 +ADD x1, x2, x2 +ADD x3, x2, x5 +ADD x2, x3, x3 +ADD x1, x1, x3 +ADD x2, x0, x1 +ADD x5, x4, x1 +ADD x2, x2, x2 +ADD x2, x3, x4 +ADD x2, x4, x5 +ADD x2, x2, x5 +ADD x4, x5, x3 +ADD x1, x1, x2 +ADD x3, x5, x2 +ADD x2, x0, x1 +ADD x1, x2, x2 +ADD x5, x1, x5 +ADD x4, x1, x2 +ADD x4, x3, x5 +ADD x5, x2, x4 +ADD x5, x0, x4 +ADD x4, x4, x2 +ADD x5, x5, x5 +ADD x3, x5, x2 +ADD x1, x4, x4 +ADD x1, x4, x4 +ADD x2, x1, x3 +ADD x1, x2, x4 +ADD x5, x2, x5 +ADD x4, x1, x1 +ADD x4, x5, x2 +ADD x3, x4, x3 +ADD x3, x5, x5 +ADD x1, x5, x1 +ADD x2, x3, x1 +ADD x3, x0, x3 +ADD x2, x0, x1 +ADD x3, x5, x3 +ADD x5, x0, x5 +ADD x3, x5, x4 +ADD x3, x1, x3 +ADD x2, x1, x4 +ADD x3, x0, x1 +ADD x5, x2, x2 +ADD x3, x5, x4 +ADD x5, x0, x1 +ADD x5, x5, x4 +ADD x3, x1, x5 +ADD x5, x5, x4 +ADD x2, x4, x4 +ADD x3, x2, x1 +ADD x2, x4, x3 +ADD x3, x2, x5 +ADD x1, x3, x4 +ADD x2, x3, x2 +ADD x5, x2, x3 +ADD x5, x5, x4 +ADD x4, x1, x5 +ADD x5, x0, x2 +ADD x1, x2, x5 +ADD x2, x0, x1 +ADD x5, x5, x3 +ADD x3, x0, x4 +ADD x3, x3, x1 +ADD x4, x2, x5 +ADD x2, x5, x5 +ADD x2, x3, x5 +ADD x1, x4, x2 +ADD x3, x0, x4 +ADD x5, x2, x2 +ADD x4, x3, x2 +ADD x3, x1, x1 +ADD x1, x5, x4 +ADD x2, x2, x5 +ADD x5, x0, x2 +ADD x1, x2, x2 +ADD x4, x0, x5 +ADD x5, x1, x3 +ADD x2, x0, x2 +ADD x3, x4, x2 +ADD x2, x1, x3 +ADD x3, x5, x4 +ADD x1, x3, x3 +ADD x2, x0, x5 +ADD x5, x4, x1 +ADD x3, x4, x5 +ADD x4, x1, x5 +ADD x5, x5, x4 +ADD x3, x4, x2 +ADD x2, x1, x2 +ADD x4, x2, x5 +ADD x2, x3, x3 +ADD x4, x1, x2 +ADD x2, x1, x5 +ADD x2, x3, x3 +ADD x4, x5, x3 +ADD x4, x5, x4 +ADD x5, x3, x2 +ADD x5, x2, x5 +ADD x5, x5, x4 +ADD x5, x3, x5 +ADD x5, x0, x1 +ADD x1, x1, x1 +ADD x3, x2, x1 +ADD x4, x0, x4 +ADD x2, x1, x2 +ADD x4, x3, x3 +ADD x3, x4, x1 +ADD x2, x4, x1 +ADD x5, x4, x2 +ADD x5, x5, x4 +ADD x4, x0, x3 +ADD x2, x0, x2 +ADD x2, x2, x2 +ADD x5, x2, x3 +ADD x1, x1, x5 +ADD x3, x4, x4 +ADD x4, x3, x4 +ADD x4, x3, x5 +ADD x5, x1, x1 +ADD x3, x3, x5 +ADD x2, x0, x1 +ADD x2, x3, x5 +ADD x5, x3, x2 +ADD x2, x1, x1 +ADD x1, x1, x5 +ADD x3, x2, x4 +ADD x3, x4, x3 +ADD x1, x2, x4 +ADD x5, x4, x3 +ADD x1, x3, x1 +ADD x5, x1, x5 +ADD x1, x1, x1 +ADD x4, x5, x3 +ADD x4, x2, x3 +ADD x3, x1, x3 +ADD x1, x2, x1 +ADD x5, x0, x3 +ADD x3, x5, x1 +ADD x5, x4, x2 +ADD x2, x4, x2 +ADD x4, x4, x4 +ADD x4, x0, x3 +ADD x3, x5, x3 +ADD x1, x2, x2 +ADD x1, x1, x3 +ADD x2, x1, x5 +ADD x1, x2, x5 +ADD x5, x5, x4 +ADD x4, x5, x5 +ADD x2, x4, x5 +ADD x5, x5, x4 +ADD x1, x4, x2 +ADD x4, x2, x5 +ADD x5, x1, x2 +ADD x2, x4, x5 +ADD x2, x5, x1 +ADD x2, x4, x1 +ADD x2, x0, x1 +ADD x3, x1, x2 +ADD x1, x4, x4 +ADD x3, x4, x1 +ADD x3, x0, x5 +ADD x3, x0, x1 +ADD x2, x5, x1 +ADD x3, x2, x3 +ADD x2, x3, x4 +ADD x4, x0, x1 +ADD x5, x3, x5 +ADD x2, x4, x5 +ADD x1, x5, x1 +ADD x3, x1, x2 +ADD x5, x0, x5 +ADD x3, x1, x3 +ADD x1, x0, x4 +ADD x4, x4, x3 +ADD x1, x3, x3 +ADD x1, x3, x2 +ADD x2, x1, x3 +ADD x2, x5, x5 +ADD x4, x4, x3 +ADD x5, x3, x4 +ADD x1, x1, x2 +ADD x3, x2, x2 +ADD x4, x0, x5 +ADD x2, x4, x3 +ADD x2, x2, x1 +ADD x2, x2, x1 +ADD x1, x4, x1 +ADD x4, x0, x2 +ADD x1, x0, x4 +ADD x5, x4, x5 +ADD x1, x1, x2 +ADD x5, x2, x3 +ADD x4, x4, x5 +ADD x1, x0, x2 +ADD x1, x3, x2 +ADD x1, x2, x2 +ADD x4, x2, x4 +ADD x5, x2, x5 +ADD x4, x3, x3 +ADD x4, x4, x5 +ADD x2, x3, x4 +ADD x5, x5, x3 +ADD x5, x5, x1 +ADD x3, x0, x4 +ADD x3, x5, x2 +ADD x4, x0, x1 +ADD x4, x2, x3 +ADD x2, x3, x5 +ADD x2, x0, x1 +ADD x3, x2, x5 +ADD x4, x3, x2 +ADD x4, x2, x5 +ADD x4, x4, x5 +ADD x1, x4, x5 +ADD x5, x2, x2 +ADD x5, x2, x2 +ADD x3, x2, x4 +ADD x4, x4, x1 +ADD x2, x4, x3 +ADD x3, x4, x5 +ADD x4, x3, x3 +ADD x4, x5, x5 +ADD x1, x2, x1 +ADD x4, x4, x5 +ADD x2, x3, x3 +ADD x3, x2, x3 +ADD x1, x2, x3 +ADD x3, x2, x3 +ADD x4, x3, x5 +ADD x2, x4, x1 +ADD x3, x3, x2 +ADD x1, x2, x1 +ADD x1, x2, x3 +ADD x3, x5, x1 +ADD x2, x3, x2 +ADD x3, x0, x1 +ADD x4, x3, x3 +ADD x2, x4, x5 +ADD x4, x0, x2 +ADD x5, x0, x5 +ADD x4, x4, x2 +ADD x3, x1, x3 +ADD x3, x2, x2 +ADD x4, x0, x3 +ADD x1, x2, x4 +ADD x2, x4, x2 +ADD x3, x1, x5 +ADD x1, x0, x2 +ADD x5, x3, x3 +ADD x2, x5, x3 +ADD x2, x4, x3 +ADD x1, x3, x4 +ADD x1, x5, x4 +ADD x2, x3, x4 +ADD x4, x1, x5 +ADD x4, x0, x3 +ADD x4, x3, x4 +ADD x1, x4, x3 +ADD x2, x0, x1 +ADD x5, x3, x1 +ADD x5, x5, x1 +ADD x5, x1, x4 +ADD x2, x1, x3 +ADD x2, x3, x4 +ADD x4, x2, x2 +ADD x3, x5, x2 +ADD x3, x5, x1 +ADD x5, x2, x2 +ADD x5, x3, x4 +ADD x5, x2, x4 +ADD x5, x2, x3 +ADD x1, x2, x3 +ADD x3, x5, x2 +ADD x1, x0, x2 +ADD x4, x0, x3 +ADD x1, x2, x1 +ADD x3, x2, x4 +ADD x3, x3, x3 +ADD x5, x3, x4 +ADD x4, x4, x4 +ADD x4, x5, x2 +ADD x5, x1, x1 +ADD x3, x1, x3 +ADD x1, x0, x3 +ADD x5, x1, x1 +ADD x3, x4, x1 +ADD x2, x3, x1 +ADD x2, x5, x2 +ADD x1, x1, x1 +ADD x1, x1, x1 +ADD x2, x0, x3 +ADD x2, x5, x4 +ADD x5, x5, x5 +ADD x2, x3, x4 +ADD x5, x4, x5 +ADD x2, x4, x4 +ADD x5, x4, x5 +ADD x2, x1, x5 +ADD x5, x4, x2 +ADD x4, x2, x5 +ADD x4, x2, x2 +ADD x5, x4, x4 +ADD x1, x5, x4 +ADD x4, x5, x5 +ADD x3, x2, x3 +ADD x3, x5, x5 +ADD x3, x0, x1 +ADD x1, x2, x2 +ADD x1, x4, x2 +ADD x1, x3, x3 +ADD x2, x0, x2 +ADD x5, x3, x2 +ADD x2, x0, x2 +ADD x5, x4, x1 +ADD x2, x4, x4 +ADD x2, x4, x3 +ADD x4, x0, x3 +ADD x4, x3, x2 +ADD x4, x4, x2 +ADD x5, x4, x1 +ADD x3, x4, x5 +ADD x5, x1, x1 +ADD x4, x1, x2 +ADD x4, x1, x1 +ADD x2, x5, x2 +ADD x3, x4, x4 +ADD x3, x1, x3 +ADD x2, x2, x2 +ADD x4, x3, x2 +ADD x1, x1, x2 +ADD x5, x5, x3 +ADD x4, x2, x2 +ADD x2, x5, x1 +ADD x4, x2, x4 +ADD x2, x4, x2 +ADD x2, x4, x5 +ADD x4, x4, x1 +ADD x5, x0, x2 +ADD x1, x1, x4 +ADD x1, x4, x5 +ADD x3, x3, x1 +ADD x2, x0, x4 +ADD x3, x5, x5 +ADD x1, x2, x1 +ADD x1, x4, x1 +ADD x1, x2, x2 +ADD x4, x1, x3 +ADD x2, x4, x2 +ADD x4, x0, x4 +ADD x1, x3, x2 +ADD x5, x1, x3 +ADD x5, x0, x4 +ADD x1, x3, x2 +ADD x4, x0, x1 +ADD x4, x0, x2 +ADD x5, x2, x1 +ADD x3, x4, x5 +ADD x3, x5, x3 +ADD x1, x2, x1 +ADD x4, x2, x1 +ADD x2, x1, x2 +ADD x4, x2, x4 +ADD x2, x1, x3 +ADD x2, x5, x2 +ADD x4, x2, x4 +ADD x2, x5, x1 +ADD x1, x2, x2 +ADD x5, x2, x2 +ADD x3, x3, x3 +ADD x3, x5, x4 +ADD x4, x3, x3 +ADD x5, x2, x2 +ADD x2, x5, x4 +ADD x3, x0, x3 +ADD x4, x4, x5 +ADD x1, x3, x2 +ADD x2, x4, x3 +ADD x3, x2, x5 +ADD x1, x5, x3 +ADD x5, x5, x3 +ADD x2, x5, x5 +ADD x5, x2, x1 +ADD x2, x2, x5 +ADD x4, x2, x2 +ADD x3, x4, x4 +ADD x4, x5, x4 +ADD x1, x1, x5 +ADD x4, x0, x3 +ADD x5, x4, x4 +ADD x2, x2, x2 +ADD x5, x2, x3 +ADD x1, x2, x5 +ADD x1, x2, x4 +ADD x3, x3, x2 +ADD x3, x0, x5 +ADD x5, x2, x1 +ADD x2, x4, x4 +ADD x3, x5, x4 +ADD x2, x3, x1 +ADD x1, x3, x1 +ADD x2, x0, x3 +ADD x2, x0, x1 +ADD x2, x1, x2 +ADD x2, x0, x5 +ADD x5, x5, x2 +ADD x2, x2, x1 +ADD x5, x1, x1 +ADD x3, x0, x5 +ADD x5, x1, x1 +ADD x5, x5, x5 +sd x1, 0(x8) +sd x2, 8(x8) +sd x3, 16(x8) +sd x4, 24(x8) +sd x5, 32(x8) +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN + + +signature_x8_0: + .fill 0*(XLEN/32),4,0xdeadbeef + + +signature_x8_1: + .fill 19*(XLEN/32),4,0xdeadbeef + + +signature_x1_0: + .fill 256*(XLEN/32),4,0xdeadbeef + + +signature_x1_1: + .fill 256*(XLEN/32),4,0xdeadbeef + + +signature_x1_2: + .fill 148*(XLEN/32),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine + +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef + +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*(XLEN/32),4,0xdeadbeef + +#endif + +RVMODEL_DATA_END +// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/PIPELINE.S +// David_Harris@hmc.edu From e4cf044932a63d9758e2c5dcc54a4cea7e520184 Mon Sep 17 00:00:00 2001 From: bbracker Date: Tue, 2 Nov 2021 21:19:12 -0700 Subject: [PATCH 06/12] fix testbench interrupt timing --- wally-pipelined/regression/linux-wave.do | 39 +-- wally-pipelined/testbench/testbench-linux.sv | 302 ++++++++++++------- 2 files changed, 210 insertions(+), 131 deletions(-) diff --git a/wally-pipelined/regression/linux-wave.do b/wally-pipelined/regression/linux-wave.do index 30c2b0365..d2350d0ec 100644 --- a/wally-pipelined/regression/linux-wave.do +++ b/wally-pipelined/regression/linux-wave.do @@ -60,20 +60,26 @@ add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D -add wave -noupdate -group {Execution Stage} /testbench/dut/hart/ifu/PCE -add wave -noupdate -group {Execution Stage} /testbench/InstrEName -add wave -noupdate -group {Execution Stage} /testbench/dut/hart/ifu/InstrE -add wave -noupdate -group {Execution Stage} -color {Cornflower Blue} /testbench/FunctionName/FunctionName -add wave -noupdate -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrValidM -add wave -noupdate -group {Memory Stage} /testbench/dut/hart/PCM -add wave -noupdate -group {Memory Stage} /testbench/InstrMName -add wave -noupdate -group {Memory Stage} /testbench/dut/hart/InstrM -add wave -noupdate -group {Memory Stage} /testbench/dut/hart/lsu/MemAdrM -add wave -noupdate -group {WriteBack stage} /testbench/PCW -add wave -noupdate -group {WriteBack stage} /testbench/InstrW -add wave -noupdate -group {WriteBack stage} /testbench/InstrWName -add wave -noupdate -group {WriteBack stage} /testbench/InstrValidW -add wave -noupdate -group {WriteBack stage} /testbench/checkInstrW +add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE +add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE +add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName +add wave -noupdate -expand -group {Execution Stage} /testbench/textE +add wave -noupdate -expand -group {Execution Stage} -color {Cornflower Blue} /testbench/FunctionName/FunctionName +add wave -noupdate -expand -group {Memory Stage} /testbench/checkInstrM +add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrValidM +add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/PCM +add wave -noupdate -expand -group {Memory Stage} /testbench/ExpectedPCM +add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM +add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName +add wave -noupdate -expand -group {Memory Stage} /testbench/textM +add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/MemAdrM +add wave -noupdate -expand -group {WriteBack stage} /testbench/checkInstrW +add wave -noupdate -expand -group {WriteBack stage} /testbench/InstrValidW +add wave -noupdate -expand -group {WriteBack stage} /testbench/PCW +add wave -noupdate -expand -group {WriteBack stage} /testbench/ExpectedPCW +add wave -noupdate -expand -group {WriteBack stage} /testbench/InstrW +add wave -noupdate -expand -group {WriteBack stage} /testbench/InstrWName +add wave -noupdate -expand -group {WriteBack stage} /testbench/textW add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]} @@ -484,7 +490,6 @@ add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/hart/p add wave -noupdate -group {debug trace} -expand -group mem /testbench/checkInstrM add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/hart/PCM add wave -noupdate -group {debug trace} -expand -group mem /testbench/ExpectedPCM -add wave -noupdate -group {debug trace} -expand -group mem /testbench/line add wave -noupdate -group {debug trace} -expand -group mem /testbench/textM add wave -noupdate -group {debug trace} -expand -group mem -color Brown /testbench/dut/hart/hzu/TrapM add wave -noupdate -group {debug trace} -expand -group wb /testbench/checkInstrW @@ -510,7 +515,7 @@ add wave -noupdate /testbench/dut/uncore/dtim/memwrite add wave -noupdate /testbench/dut/uncore/dtim/HWDATA add wave -noupdate /testbench/dut/uncore/dtim/risingHREADYTim TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 23} {209183247 ns} 0} {{Cursor 5} {229 ns} 0} +WaveRestoreCursors {{Cursor 23} {209183247 ns} 0} {{Cursor 5} {5672440 ns} 0} quietly wave cursor active 2 configure wave -namecolwidth 250 configure wave -valuecolwidth 314 @@ -526,4 +531,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {182 ns} {330 ns} +WaveRestoreZoom {5672937 ns} {5673085 ns} diff --git a/wally-pipelined/testbench/testbench-linux.sv b/wally-pipelined/testbench/testbench-linux.sv index 72adf589b..72061f9ea 100644 --- a/wally-pipelined/testbench/testbench-linux.sv +++ b/wally-pipelined/testbench/testbench-linux.sv @@ -103,30 +103,35 @@ module testbench(); string checkpointDir; logic [1:0] initPriv; // Signals used to parse the trace file - integer data_file_all; - string name; - integer matchCount; - string line; - logic [`XLEN-1:0] ExpectedPCM; - logic [31:0] ExpectedInstrM; - string textM; - string token; - string ExpectedTokens [31:0]; - integer index; - integer StartIndex, EndIndex; - integer TokenIndex; - integer MarkerIndex; - integer NumCSRM; + `define DECLARE_TRACE_SCANNER_SIGNALS(STAGE) \ + integer traceFile``STAGE; \ + integer matchCount``STAGE; \ + string line``STAGE; \ + string token``STAGE; \ + string ExpectedTokens``STAGE [31:0]; \ + integer index``STAGE; \ + integer StartIndex``STAGE, EndIndex``STAGE; \ + integer TokenIndex``STAGE; \ + integer MarkerIndex``STAGE; \ + integer NumCSR``STAGE; \ + logic [`XLEN-1:0] ExpectedPC``STAGE; \ + logic [31:0] ExpectedInstr``STAGE; \ + string text``STAGE; \ + string MemOp``STAGE; \ + string RegWrite``STAGE; \ + integer ExpectedRegAdr``STAGE; \ + logic [`XLEN-1:0] ExpectedRegValue``STAGE; \ + logic [`XLEN-1:0] ExpectedMemAdr``STAGE, ExpectedMemReadData``STAGE, ExpectedMemWriteData``STAGE; \ + string ExpectedCSRArray``STAGE[10:0]; \ + logic [`XLEN-1:0] ExpectedCSRArrayValue``STAGE[10:0]; + `DECLARE_TRACE_SCANNER_SIGNALS(E) + `DECLARE_TRACE_SCANNER_SIGNALS(M) + integer NextMIPexpected; + integer NextMepcExpected; // Memory stage expected values from trace logic checkInstrM; integer MIPexpected; - string RegWriteM; - integer ExpectedRegAdrM; - logic [`XLEN-1:0] ExpectedRegValueM; - string MemOpM; - logic [`XLEN-1:0] ExpectedMemAdrM, ExpectedMemReadDataM, ExpectedMemWriteDataM; - string ExpectedCSRArrayM[10:0]; - logic [`XLEN-1:0] ExpectedCSRArrayValueM[10:0]; + string name; logic [`AHBW-1:0] readDataExpected; // Write back stage expected values from trace logic checkInstrW; @@ -148,6 +153,11 @@ module testbench(); integer NumCSRPostWIndex; logic [`XLEN-1:0] InstrCountW; integer RequestDelayedMIP; + integer ForceMIPFuture; + integer CSRIndex; + longint MepcExpected; + integer CheckMIPFutureE; + integer CheckMIPFutureM; // Useful Aliases `define RF dut.hart.ieu.dp.regf.rf `define PC dut.hart.ifu.pcreg.q @@ -292,13 +302,15 @@ module testbench(); ProgramLabelMapFile = {`LINUX_TEST_VECTORS,"vmlinux.objdump.lab"}; if (CHECKPOINT==0) begin // normal $readmemh({`LINUX_TEST_VECTORS,"ram.txt"}, dut.uncore.dtim.RAM); - data_file_all = $fopen({`LINUX_TEST_VECTORS,"all.txt"}, "r"); + traceFileM = $fopen({`LINUX_TEST_VECTORS,"all.txt"}, "r"); + traceFileE = $fopen({`LINUX_TEST_VECTORS,"all.txt"}, "r"); InstrCountW = '0; end else begin // checkpoint $sformat(checkpointDir,"checkpoint%0d/",CHECKPOINT); checkpointDir = {`LINUX_TEST_VECTORS,checkpointDir}; $readmemh({checkpointDir,"ram.txt"}, dut.uncore.dtim.RAM); - data_file_all = $fopen({checkpointDir,"all.txt"}, "r"); + traceFileE = $fopen({checkpointDir,"all.txt"}, "r"); + traceFileM = $fopen({checkpointDir,"all.txt"}, "r"); InstrCountW = CHECKPOINT; // manual checkpoint initializations that don't neatly fit into MACRO force {`STATUS_TSR,`STATUS_TW,`STATUS_TVM,`STATUS_MXR,`STATUS_SUM,`STATUS_MPRV} = initMSTATUS[0][22:17]; @@ -319,8 +331,12 @@ module testbench(); release `INSTRET; release `CURR_PRIV; end + // Get the E-stage trace reader ahead of the M-stage trace reader + matchCountE = $fgets(lineE,traceFileE); end + + /////////////////////////////////////////////////////////////////////////////// //////////////////////////////////// CORE ///////////////////////////////////// /////////////////////////////////////////////////////////////////////////////// @@ -332,94 +348,158 @@ module testbench(); // on the next falling edge the expected state is compared to the wally state. // step 0: read the expected state - assign checkInstrM = dut.hart.ieu.InstrValidM & ~dut.hart.priv.trap.InstrPageFaultM & ~dut.hart.priv.trap.InterruptM & ~dut.hart.StallM; + assign checkInstrM = dut.hart.ieu.InstrValidM & ~dut.hart.priv.trap.InstrPageFaultM & ~dut.hart.priv.trap.InterruptM & ~dut.hart.StallM; + `define SCAN_NEW_INSTR_FROM_TRACE(STAGE) \ + // always check PC, instruction bits \ + if (checkInstrM) begin \ + // read 1 line of the trace file \ + matchCount``STAGE = $fgets(line``STAGE, traceFile``STAGE); \ + if(`DEBUG_TRACE >= 5) $display("Time %t, line %x", $time, line``STAGE); \ + // extract PC, Instr \ + matchCount``STAGE = $sscanf(line``STAGE, "%x %x %s", ExpectedPC``STAGE, ExpectedInstr``STAGE, text``STAGE); \ + \ + // for the life of me I cannot get any build in C or C++ string parsing functions/methods to work. \ + // strtok was the best idea but it cannot be used correctly as system verilog does not have null \ + // terminated strings. \ + \ + // Just going to do this char by char. \ + StartIndex``STAGE = 0; \ + TokenIndex``STAGE = 0; \ + //$display("len = %d", line``STAGE.len()); \ + for(index``STAGE = 0; index``STAGE < line``STAGE.len(); index``STAGE++) begin \ + //$display("char = %s", line``STAGE[index]); \ + if (line``STAGE[index``STAGE] == " " || line``STAGE[index``STAGE] == "\n") begin \ + EndIndex``STAGE = index``STAGE; \ + ExpectedTokens``STAGE[TokenIndex``STAGE] = line``STAGE.substr(StartIndex``STAGE, EndIndex``STAGE-1); \ + //$display("In Tokenizer %s", line``STAGE.substr(StartIndex, EndIndex-1)); \ + StartIndex``STAGE = EndIndex``STAGE + 1; \ + TokenIndex``STAGE++; \ + end \ + end \ + \ + MarkerIndex``STAGE = 3; \ + NumCSR``STAGE = 0; \ + MemOp``STAGE = ""; \ + RegWrite``STAGE = ""; \ + \ + #2; \ + \ + while(TokenIndex``STAGE > MarkerIndex``STAGE) begin \ + // parse the GPR \ + if (ExpectedTokens``STAGE[MarkerIndex``STAGE] == "GPR") begin \ + RegWrite``STAGE = ExpectedTokens``STAGE[MarkerIndex``STAGE]; \ + matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE+1], "%d", ExpectedRegAdr``STAGE); \ + matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE+2], "%x", ExpectedRegValue``STAGE); \ + MarkerIndex``STAGE += 3; \ + // parse memory address, read data, and/or write data \ + end else if(ExpectedTokens``STAGE[MarkerIndex``STAGE].substr(0, 2) == "Mem") begin \ + MemOp``STAGE = ExpectedTokens``STAGE[MarkerIndex``STAGE]; \ + matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE+1], "%x", ExpectedMemAdr``STAGE); \ + matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE+2], "%x", ExpectedMemWriteData``STAGE); \ + matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE+3], "%x", ExpectedMemReadData``STAGE); \ + MarkerIndex``STAGE += 4; \ + // parse CSRs, because there are 1 or more CSRs after the CSR token \ + // we check if the CSR token or the number of CSRs is greater than 0. \ + // if so then we want to parse for a CSR. \ + end else if(ExpectedTokens``STAGE[MarkerIndex``STAGE] == "CSR" || NumCSR``STAGE > 0) begin \ + if(ExpectedTokens``STAGE[MarkerIndex``STAGE] == "CSR") begin \ + // all additional CSR's won't have this token. \ + MarkerIndex``STAGE++; \ + end \ + matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE], "%s", ExpectedCSRArray``STAGE[NumCSR``STAGE]); \ + matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE+1], "%x", ExpectedCSRArrayValue``STAGE[NumCSR``STAGE]); \ + MarkerIndex``STAGE += 2; \ + if(`"STAGE`"=="E") begin \ + // match MIP to QEMU's because interrupts are imprecise \ + if(ExpectedCSRArrayE[NumCSRE].substr(0, 2) == "mip") begin \ + CheckMIPFutureE = 1; \ + NextMIPexpected = ExpectedCSRArrayValueE[NumCSRE]; \ + end \ + // $display("%tn: ExpectedCSRArrayM[7] (MEPC) = %x",$time,ExpectedCSRArrayM[7]); \ + // $display("%tn: ExpectedPCM = %x",$time,ExpectedPCM); \ + // // if PC does not equal MEPC, request delayed MIP is True \ + // if(ExpectedPCM != ExpectedCSRArrayM[7]) begin \ + // RequestDelayedMIP = 1; \ + // end else begin \ + // $display("%tns: Updating MIP to %x",$time,ExpectedCSRArrayValueM[NumCSRM]); \ + // MIPexpected = ExpectedCSRArrayValueM[NumCSRM]; \ + // force dut.hart.priv.csr.genblk1.csri.MIP_REGW = MIPexpected; \ + // end \ + // end \ + // $display("%tns: ExpectedCSRArrayM::: %p",$time,ExpectedCSRArrayM); \ + if(ExpectedCSRArrayE[NumCSRE].substr(0,3) == "mepc") begin \ + $display("hello! we are here."); \ + MepcExpected = ExpectedCSRArrayValueE[NumCSRE]; \ + $display("%tns: MepcExpected: %x",$time,MepcExpected); \ + end \ + end \ + \ + NumCSR``STAGE++; \ + end \ + end \ + if(`"STAGE`"=="M") begin \ + // override on special conditions \ + if (ExpectedMemAdrM == 'h10000005) begin \ + //$display("%tns, %d instrs: Overwriting read data from CLINT.", $time, InstrCountW); \ + force dut.hart.ieu.dp.ReadDataM = ExpectedMemReadDataM; \ + end \ + if(textM.substr(0,5) == "rdtime") begin \ + //$display("%tns, %d instrs: Overwrite MTIME_CLINT on read of MTIME in memory stage.", $time, InstrCountW); \ + force dut.uncore.clint.clint.MTIME = ExpectedRegValueM; \ + end \ + end \ + end \ + always @(negedge clk) begin - // always check PC, instruction bits - if (checkInstrM) begin - // read 1 line of the trace file - matchCount = $fgets(line, data_file_all); - if(`DEBUG_TRACE >= 5) $display("Time %t, line %x", $time, line); - // extract PC, Instr - matchCount = $sscanf(line, "%x %x %s", ExpectedPCM, ExpectedInstrM, textM); - //$display("matchCount %d, PCM %x ExpectedInstrM %x textM %x", matchCount, ExpectedPCM, ExpectedInstrM, textM); + `SCAN_NEW_INSTR_FROM_TRACE(E) + end - // for the life of me I cannot get any build in C or C++ string parsing functions/methods to work. - // strtok was the best idea but it cannot be used correctly as system verilog does not have null - // terminated strings. - - // Just going to do this char by char. - StartIndex = 0; - TokenIndex = 0; - //$display("len = %d", line.len()); - for(index = 0; index < line.len(); index++) begin - //$display("char = %s", line[index]); - if (line[index] == " " || line[index] == "\n") begin - EndIndex = index; - ExpectedTokens[TokenIndex] = line.substr(StartIndex, EndIndex-1); - //$display("In Tokenizer %s", line.substr(StartIndex, EndIndex-1)); - StartIndex = EndIndex + 1; - TokenIndex++; - end + always @(negedge clk) begin + `SCAN_NEW_INSTR_FROM_TRACE(M) + end + + // MIP spoofing + always @(posedge clk) begin + #1; + if(CheckMIPFutureE) CheckMIPFutureE <= 0; + CheckMIPFutureM <= CheckMIPFutureE; + if(CheckMIPFutureM) begin + if((ExpectedPCM != MepcExpected) & ((MepcExpected - ExpectedPCM) * (MepcExpected - ExpectedPCM) <= 16)) begin + RequestDelayedMIP = 1; + $display("%tns: Requesting Delayed MIP. Current MEPC value is %x",$time,MepcExpected); + end else begin // update MIP immediately + $display("%tns: Updating MIP to %x",$time,NextMIPexpected); + MIPexpected = NextMIPexpected; + force dut.hart.priv.csr.genblk1.csri.MIP_REGW = MIPexpected; end - - MarkerIndex = 3; - NumCSRM = 0; - MemOpM = ""; - RegWriteM = ""; - - #2; - - while(TokenIndex > MarkerIndex) begin - // parse the GPR - if (ExpectedTokens[MarkerIndex] == "GPR") begin - RegWriteM = ExpectedTokens[MarkerIndex]; - matchCount = $sscanf(ExpectedTokens[MarkerIndex+1], "%d", ExpectedRegAdrM); - matchCount = $sscanf(ExpectedTokens[MarkerIndex+2], "%x", ExpectedRegValueM); - MarkerIndex += 3; - // parse memory address, read data, and/or write data - end else if(ExpectedTokens[MarkerIndex].substr(0, 2) == "Mem") begin - MemOpM = ExpectedTokens[MarkerIndex]; - matchCount = $sscanf(ExpectedTokens[MarkerIndex+1], "%x", ExpectedMemAdrM); - matchCount = $sscanf(ExpectedTokens[MarkerIndex+2], "%x", ExpectedMemWriteDataM); - matchCount = $sscanf(ExpectedTokens[MarkerIndex+3], "%x", ExpectedMemReadDataM); - MarkerIndex += 4; - // parse CSRs, because there are 1 or more CSRs after the CSR token - // we check if the CSR token or the number of CSRs is greater than 0. - // if so then we want to parse for a CSR. - end else if(ExpectedTokens[MarkerIndex] == "CSR" || NumCSRM > 0) begin - if(ExpectedTokens[MarkerIndex] == "CSR") begin - // all additional CSR's won't have this token. - MarkerIndex++; - end - matchCount = $sscanf(ExpectedTokens[MarkerIndex], "%s", ExpectedCSRArrayM[NumCSRM]); - matchCount = $sscanf(ExpectedTokens[MarkerIndex+1], "%x", ExpectedCSRArrayValueM[NumCSRM]); - MarkerIndex += 2; - // match MIP to QEMU's because interrupts are imprecise - if(ExpectedCSRArrayM[NumCSRM].substr(0, 2) == "mip") begin - $display("%tn: ExpectedCSRArrayM[7] (MEPC) = %x",$time,ExpectedCSRArrayM[7]); - $display("%tn: ExpectedPCM = %x",$time,ExpectedPCM); - // if PC does not equal MEPC, request delayed MIP is True - if(ExpectedPCM != ExpectedCSRArrayM[7]) begin - RequestDelayedMIP = 1; - end else begin - $display("%tns: Updating MIP to %x",$time,ExpectedCSRArrayValueM[NumCSRM]); - MIPexpected = ExpectedCSRArrayValueM[NumCSRM]; - force dut.hart.priv.csr.genblk1.csri.MIP_REGW = MIPexpected; - end - end - NumCSRM++; - end - end - // override on special conditions - if (ExpectedMemAdrM == 'h10000005) begin - //$display("%tns, %d instrs: Overwriting read data from CLINT.", $time, InstrCountW); - force dut.hart.ieu.dp.ReadDataM = ExpectedMemReadDataM; - end - if(textM.substr(0,5) == "rdtime") begin - //$display("%tns, %d instrs: Overwrite MTIME_CLINT on read of MTIME in memory stage.", $time, InstrCountW); - force dut.uncore.clint.clint.MTIME = ExpectedRegValueM; + $display("%tn: ExpectedCSRArrayM = %p",$time,ExpectedCSRArrayM); + $display("%tn: ExpectedCSRArrayValueM = %p",$time,ExpectedCSRArrayValueM); + $display("%tn: ExpectedTokens = %p",$time,ExpectedTokensM); + $display("%tn: MepcExpected = %x",$time,MepcExpected); + $display("%tn: ExpectedPCM = %x",$time,ExpectedPCM); + // if PC does not equal MEPC, request delayed MIP is True + $display("%tns: Difference/multiplication thing: %x",$time,(MepcExpected - ExpectedPCM) * (MepcExpected - ExpectedPCM)); + $display("%tn: ExpectedCSRArrayM[NumCSRM] %x",$time,ExpectedCSRArrayM[NumCSRM]); + $display("%tn: ExpectedCSRArrayValueM[NumCSRM] %x",$time,ExpectedCSRArrayValueM[NumCSRM]); + + if((ExpectedPCM != MepcExpected) & ((MepcExpected - ExpectedPCM) * (MepcExpected - ExpectedPCM) <= 16)) begin + RequestDelayedMIP = 1; + $display("%tns: Requesting Delayed MIP. Current MEPC value is %x",$time,MepcExpected); + end else begin + $display("%tns: Updating MIP to %x",$time,NextMIPexpected); + MIPexpected = NextMIPexpected; + force dut.hart.priv.csr.genblk1.csri.MIP_REGW = MIPexpected; end end + if(RequestDelayedMIP) begin + $display("%tns: Executing Delayed MIP. Current MEPC value is %x",$time,dut.hart.priv.csr.genblk1.csrm.MEPC_REGW); + $display("%tns: Updating MIP to %x",$time,NextMIPexpected); + $display("%tns: MepcExpected %x",$time,MepcExpected); + MIPexpected = NextMIPexpected; + force dut.hart.priv.csr.genblk1.csri.MIP_REGW = MIPexpected; + $display("%tns: Finished Executing Delayed MIP. Current MEPC value is %x",$time,dut.hart.priv.csr.genblk1.csrm.MEPC_REGW); + RequestDelayedMIP = 0; + end end // step 1: register expected state into the write back stage. @@ -449,7 +529,7 @@ module testbench(); ExpectedMemWriteDataW <= '0; ExpectedMemReadDataW <= '0; NumCSRW <= '0; - end else begin + end else if (dut.hart.ieu.c.InstrValidM) begin ExpectedPCW <= ExpectedPCM; ExpectedInstrW <= ExpectedInstrM; textW <= textM; @@ -484,12 +564,6 @@ module testbench(); // step2: make all checks in the write back stage. assign checkInstrW = InstrValidW & ~dut.hart.StallW; // trapW will already be invalid in there was an InstrPageFault in the previous instruction. always @(negedge clk) begin - if(RequestDelayedMIP) begin - $display("%tns: Updating MIP to %x",$time,ExpectedCSRArrayValueW[NumCSRM]); - MIPexpected = ExpectedCSRArrayValueW[NumCSRM]; - force dut.hart.priv.csr.genblk1.csri.MIP_REGW = MIPexpected; - RequestDelayedMIP = 0; - end // always check PC, instruction bits if (checkInstrW) begin InstrCountW += 1; @@ -521,7 +595,7 @@ module testbench(); if(MemOpW == "MemR" || MemOpW == "MemRW") begin if(`DEBUG_TRACE >= 4) $display("\tReadDataW: %016x ? expected: %016x", dut.hart.ieu.dp.ReadDataW, ExpectedMemReadDataW); `checkEQ("ReadDataW",dut.hart.ieu.dp.ReadDataW,ExpectedMemReadDataW) - end else if(ExpectedTokens[MarkerIndex] == "MemW" || ExpectedTokens[MarkerIndex] == "MemRW") begin + end else if(MemOpW == "MemW" || MemOpW == "MemRW") begin if(`DEBUG_TRACE >= 4) $display("\tWriteDataW: %016x ? expected: %016x", WriteDataW, ExpectedMemWriteDataW); `checkEQ("WriteDataW",ExpectedMemWriteDataW,ExpectedMemWriteDataW) end From 5fc12d4ae938b822ba18f55c0c54d6200e06202b Mon Sep 17 00:00:00 2001 From: slmnemo Date: Wed, 3 Nov 2021 01:50:00 -0700 Subject: [PATCH 07/12] edited to include missing instructions added cd tests before cd imperas-riscv-tests to reflect new tests folder modified cd ../addins so we can point to it from the new imperas-riscv-tests within the tests folder added instructions so the buildroot test exists --- README.md | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/README.md b/README.md index 975b8f141..36fbbb4f9 100644 --- a/README.md +++ b/README.md @@ -8,9 +8,10 @@ To use Wally on Linux: ``` git clone https://github.com/davidharrishmc/riscv-wally cd riscv-wally +cd tests cd imperas-riscv-tests make -cd ../addins +cd ../../addins git clone https://github.com/riscv-non-isa/riscv-arch-test git clone https://github.com/riscv-software-src/riscv-isa-sim cd riscv-isa-sim @@ -32,6 +33,8 @@ edit Makefile.include make make XLEN=32 exe2memfile.pl work/*/*/*.elf # converts ELF files to a format that can be read by Modelsim +cd ../../wally-pipelined/linux-testgen/linux-testvectors +./tvLinker.sh ``` Notes: From b34569c358de566a280efb8eb7704f4309d34f4a Mon Sep 17 00:00:00 2001 From: Kevin Date: Wed, 3 Nov 2021 10:49:34 -0700 Subject: [PATCH 08/12] changed code aligner to run recursively on a root directory -only runs the aligner on .sv files -runs recursively on sub-directories --- wally-pipelined/src/ifu/CodeAligner.py | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/wally-pipelined/src/ifu/CodeAligner.py b/wally-pipelined/src/ifu/CodeAligner.py index 59f9de4e8..579fd6237 100644 --- a/wally-pipelined/src/ifu/CodeAligner.py +++ b/wally-pipelined/src/ifu/CodeAligner.py @@ -87,12 +87,26 @@ def Mod_Space_at(Ln,loc,diff): return NewString -def main_filehandler(overwrite=False): +'''def main_filehandler(overwrite=False): for filename in os.listdir(): - if ".py" not in filename: + if ".sv" in filename: GiantString = read_input(filename) SOV = ID_start(GiantString) ModifiedGS = modified_logNew(GiantString,SOV) - Newname = write_to_output(filename,ModifiedGS,overwrite) + Newname = write_to_output(filename,ModifiedGS,overwrite)''' +def root_filehandler(path,overwrite=False): + for f in os.listdir(path): + if os.path.isdir(f): + root_filehandler(path+"/"+f) + else: + if ".sv" in f: + GiantString = read_input(f) + SOV = ID_start(GiantString) + ModifiedGS = modified_logNew(GiantString,SOV) + Newname = write_to_output(f,ModifiedGS,overwrite) + + +def driver(overwrite=False): + root_filehandler(os.getcwd()) -main_filehandler(True) \ No newline at end of file +driver(True) \ No newline at end of file From d957d86f3bf6c4e7588ce1827ed8c00be1ed8891 Mon Sep 17 00:00:00 2001 From: davidharrishmc <74973295+davidharrishmc@users.noreply.github.com> Date: Wed, 3 Nov 2021 13:30:21 -0700 Subject: [PATCH 09/12] added wally-riscv-arch-test compile commands --- README.md | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/README.md b/README.md index 36fbbb4f9..2de55cbc5 100644 --- a/README.md +++ b/README.md @@ -8,10 +8,8 @@ To use Wally on Linux: ``` git clone https://github.com/davidharrishmc/riscv-wally cd riscv-wally -cd tests -cd imperas-riscv-tests -make -cd ../../addins +cd addins +*** can these clones be replaced with git submodule commands? git clone https://github.com/riscv-non-isa/riscv-arch-test git clone https://github.com/riscv-software-src/riscv-isa-sim cd riscv-isa-sim @@ -33,6 +31,13 @@ edit Makefile.include make make XLEN=32 exe2memfile.pl work/*/*/*.elf # converts ELF files to a format that can be read by Modelsim +cd ../../tests +cd imperas-riscv-tests +make +cd ../wally-riscv-arch-test +make +make XLEN=32 +exe2memfile.pl work/*/*/*.elf # converts ELF files to a format that can be read by Modelsim cd ../../wally-pipelined/linux-testgen/linux-testvectors ./tvLinker.sh ``` From 099c4e8b6bef9cd9e8e6b001e190a2447a05981b Mon Sep 17 00:00:00 2001 From: davidharrishmc <74973295+davidharrishmc@users.noreply.github.com> Date: Wed, 3 Nov 2021 13:40:23 -0700 Subject: [PATCH 10/12] fixed 64i --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 2de55cbc5..740f985fd 100644 --- a/README.md +++ b/README.md @@ -15,7 +15,7 @@ git clone https://github.com/riscv-software-src/riscv-isa-sim cd riscv-isa-sim cp -r arch_test_target/spike/device/rv32i_m/I arch_test_target/spike/device/rv32i_m/F -cp -r arch_test_target/spike/device/rv32i_m/I arch_test_target/spike/device/rv64i_m/D +cp -r arch_test_target/spike/device/rv64i_m/I arch_test_target/spike/device/rv64i_m/D mkdir build cd build From f540bb13c0afe70a4966c6d1906352d188589d06 Mon Sep 17 00:00:00 2001 From: davidharrishmc <74973295+davidharrishmc@users.noreply.github.com> Date: Wed, 3 Nov 2021 13:49:07 -0700 Subject: [PATCH 11/12] fixed 64i --- README.md | 1 + 1 file changed, 1 insertion(+) diff --git a/README.md b/README.md index 740f985fd..db4818723 100644 --- a/README.md +++ b/README.md @@ -13,6 +13,7 @@ cd addins git clone https://github.com/riscv-non-isa/riscv-arch-test git clone https://github.com/riscv-software-src/riscv-isa-sim cd riscv-isa-sim +*** replace these with a copy from ../install/F and ../install/D containing the Makefile.includes already updated cp -r arch_test_target/spike/device/rv32i_m/I arch_test_target/spike/device/rv32i_m/F cp -r arch_test_target/spike/device/rv64i_m/I arch_test_target/spike/device/rv64i_m/D