From 1ce0975366c46da0210f14b7fb9d23d24dc570d3 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 8 Jul 2022 08:45:21 +0000 Subject: [PATCH] Adjusting byte writes to RAM --- pipelined/src/uncore/ram.sv | 7 ++++- pipelined/src/uncore/uncore.sv | 51 +++++----------------------------- 2 files changed, 13 insertions(+), 45 deletions(-) diff --git a/pipelined/src/uncore/ram.sv b/pipelined/src/uncore/ram.sv index 7ef023fe6..39094142a 100644 --- a/pipelined/src/uncore/ram.sv +++ b/pipelined/src/uncore/ram.sv @@ -38,6 +38,7 @@ module ram #(parameter BASE=0, RANGE = 65535) ( input logic HREADY, input logic [1:0] HTRANS, input logic [`XLEN-1:0] HWDATA, + input logic [`XLEN/8-1:0] HWSTRB, input logic [3:0] HSIZED, output logic [`XLEN-1:0] HREADRam, output logic HRESPRam, HREADYRam @@ -74,8 +75,12 @@ module ram #(parameter BASE=0, RANGE = 65535) ( // *** it shoudl be centralized and sent over HWSTRB swbytemask swbytemask(.Size(HSIZED[1:0]), .Adr(HADDRD[2:0]), .ByteMask(ByteMask)); + always @(posedge HCLK) begin + assert (ByteMask == HWSTRB | ~memwriteD) else $display("HSIZED %b HADDRD %b ByteMask %b HWSTRB %b\n", HSIZED[1:0], HADDRD[2:0], ByteMask, HWSTRB); + end + // single-ported RAM bram1p1rw #(`XLEN/8, 8, ADDR_WIDTH) - memory(.clk(HCLK), .we(memwriteD), .bwe(ByteMask), .addr(RamAddr[ADDR_WIDTH+OFFSET-1:OFFSET]), .dout(HREADRam), .din(HWDATA)); + memory(.clk(HCLK), .we(memwriteD), /*.bwe(HWSTRB), */ .bwe(ByteMask), .addr(RamAddr[ADDR_WIDTH+OFFSET-1:OFFSET]), .dout(HREADRam), .din(HWDATA)); endmodule diff --git a/pipelined/src/uncore/uncore.sv b/pipelined/src/uncore/uncore.sv index f4b1202ea..0ffa17bfe 100644 --- a/pipelined/src/uncore/uncore.sv +++ b/pipelined/src/uncore/uncore.sv @@ -69,13 +69,13 @@ module uncore ( output logic [63:0] MTIME_CLINT ); - logic [`XLEN-1:0] HREADRam, HREADCLINT, HREADPLIC, HREADGPIO, HREADUART, HREADSDC; + logic [`XLEN-1:0] HREADRam, HREADSDC; logic [8:0] HSELRegions; logic HSELRam, HSELCLINT, HSELPLIC, HSELGPIO, HSELUART, HSELSDC; logic HSELEXTD, HSELRamD, HSELCLINTD, HSELPLICD, HSELGPIOD, HSELUARTD, HSELSDCD; - logic HRESPRam, HRESPCLINT, HRESPPLIC, HRESPGPIO, HRESPUART, HRESPSDC; - logic HREADYRam, HREADYCLINT, HREADYPLIC, HREADYGPIO, HREADYUART, HRESPSDCD; + logic HRESPRam, HRESPSDC; + logic HREADYRam, HRESPSDCD; logic [`XLEN-1:0] HREADBootRom; logic HSELBootRom, HSELBootRomD, HRESPBootRom, HREADYBootRom, HREADYSDC; logic HSELNoneD; @@ -120,30 +120,23 @@ module uncore ( .HCLK, .HRESETn, .HSELRam, .HADDR, .HWRITE, .HREADY, .HSIZED, - .HTRANS, .HWDATA, .HREADRam, + .HTRANS, .HWDATA, .HWSTRB, .HREADRam, .HRESPRam, .HREADYRam); end + // *** switch to new RAM if (`BOOTROM_SUPPORTED) begin : bootrom - ram_orig #(.BASE(`BOOTROM_BASE), .RANGE(`BOOTROM_RANGE)) + ram #(.BASE(`BOOTROM_BASE), .RANGE(`BOOTROM_RANGE)) bootrom( .HCLK, .HRESETn, .HSELRam(HSELBootRom), .HADDR, .HWRITE, .HREADY, .HTRANS, .HSIZED, - .HWDATA, + .HWDATA, .HWSTRB, .HREADRam(HREADBootRom), .HRESPRam(HRESPBootRom), .HREADYRam(HREADYBootRom)); end // memory-mapped I/O peripherals if (`CLINT_SUPPORTED == 1) begin : clint -/* clint clint( - .HCLK, .HRESETn, .TIMECLK, - .HSELCLINT, .HADDR(HADDR[15:0]), .HWRITE, - .HWDATA, .HREADY, .HTRANS, .HSIZED, - .HREADCLINT, - .HRESPCLINT, .HREADYCLINT, - .MTIME(MTIME_CLINT), - .MTimerInt, .MSwInt);*/ clint_apb clint( .PCLK, .PRESETn, .PSEL(PSEL[1]), .PADDR(PADDR[15:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE, .PRDATA(PRDATA[1]), .PREADY(PREADY[1]), @@ -155,13 +148,6 @@ module uncore ( assign MTimerInt = 0; assign MSwInt = 0; end if (`PLIC_SUPPORTED == 1) begin : plic -/* plic plic( - .HCLK, .HRESETn, - .HSELPLIC, .HADDR(HADDR[27:0]), - .HWRITE, .HREADY, .HTRANS, .HWDATA, - .UARTIntr, .GPIOIntr, - .HREADPLIC, .HRESPPLIC, .HREADYPLIC, - .MExtInt, .SExtInt); */ plic_apb plic( .PCLK, .PRESETn, .PSEL(PSEL[2]), .PADDR(PADDR[27:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE, .PRDATA(PRDATA[2]), .PREADY(PREADY[2]), @@ -172,17 +158,6 @@ module uncore ( assign SExtInt = 0; end if (`GPIO_SUPPORTED == 1) begin : gpio -/* gpio gpio( - .HCLK, .HRESETn, .HSELGPIO, - .HADDR(HADDR[7:0]), - .HWDATA, - .HWRITE, .HREADY, - .HTRANS, - .HREADGPIO, - .HRESPGPIO, .HREADYGPIO, - .GPIOPinsIn, - .GPIOPinsOut, .GPIOPinsEn, - .GPIOIntr); */ gpio_apb gpio( .PCLK, .PRESETn, .PSEL(PSEL[0]), .PADDR(PADDR[7:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE, .PRDATA(PRDATA[0]), .PREADY(PREADY[0]), @@ -191,15 +166,6 @@ module uncore ( assign GPIOPinsOut = 0; assign GPIOPinsEn = 0; assign GPIOIntr = 0; end if (`UART_SUPPORTED == 1) begin : uart -/* uart uart( - .HCLK, .HRESETn, - .HSELUART, - .HADDR(HADDR[2:0]), - .HWRITE, .HWDATA, - .HREADUART, .HRESPUART, .HREADYUART, - .SIN(UARTSin), .DSRb(1'b1), .DCDb(1'b1), .CTSb(1'b0), .RIb(1'b1), // from E1A driver from RS232 interface - .SOUT(UARTSout), .RTSb(), .DTRb(), // to E1A driver to RS232 interface - .OUT1b(), .OUT2b(), .INTR(UARTIntr), .TXRDYb(), .RXRDYb()); // to CPU */ uart_apb uart( .PCLK, .PRESETn, .PSEL(PSEL[3]), .PADDR(PADDR[2:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE, .PRDATA(PRDATA[3]), .PREADY(PREADY[3]), @@ -227,9 +193,6 @@ module uncore ( // AHB Read Multiplexer assign HRDATA = ({`XLEN{HSELRamD}} & HREADRam) | ({`XLEN{HSELEXTD}} & HRDATAEXT) | -// ({`XLEN{HSELCLINTD}} & HREADCLINT) | -// ({`XLEN{HSELPLICD}} & HREADPLIC) | -// ({`XLEN{HSELGPIOD}} & HREADGPIO) | ({`XLEN{HSELBRIDGED}} & HREADBRIDGE) | ({`XLEN{HSELBootRomD}} & HREADBootRom) | // ({`XLEN{HSELUARTD}} & HREADUART) |