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Ross Thompson 2022-08-31 15:40:56 -05:00
parent 2b528dc8be
commit 1cd7d8dbfe
1 changed files with 1 additions and 1 deletions
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pipelined/src/ebu/busfsm.sv
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@ -80,7 +80,7 @@ module busfsm
assign HTRANS = (BusCurrState == STATE_READY & HREADY & |RW) |
(BusCurrState == STATE_CAPTURE & ~HREADY) ? AHB_NONSEQ : AHB_IDLE;
assign HWRITE = (BusCurrState == STATE_READY) & RW[0]; // *** might not be necessary, maybe just RW[0]
assign HWRITE = RW[0];
assign CaptureEn = BusCurrState == STATE_CAPTURE;
endmodule