Merge branch 'main' into coverage3

bin/CacheSim.py

@@ -36,6 +36,9 @@
 # This helps avoid unexpected logger behavior.
 # With verbose mode off, the simulator only reports mismatches between its and Wally's behavior.
 # With verbose mode on, the simulator logs each access into the cache.
+# Add -p or --perf to report the hit/miss ratio. 
+# Add -d or --dist to report the distribution of loads, stores, and atomic ops.
+# These distributions may not add up to 100; this is because of flushes or invalidations.
 
 import sys
 import math
@@ -197,11 +200,24 @@ if __name__ == "__main__":
     parser.add_argument('taglen', type=int, help="Length of the tag in bits", metavar="T")
     parser.add_argument('-f', "--file", required=True, help="Log file to simulate from")
     parser.add_argument('-v', "--verbose", action='store_true', help="verbose/full-trace mode")
+    parser.add_argument('-p', "--perf", action='store_true', help="Report hit/miss ratio")
+    parser.add_argument('-d', "--dist", action='store_true', help="Report distribution of operations")
 
     args = parser.parse_args()
     cache = Cache(args.numlines, args.numways, args.addrlen, args.taglen)
-    #numtests = -1
     extfile = os.path.expanduser(args.file)
+    nofails = True
+
+    if args.perf:
+        hits = 0
+        misses = 0
+
+    if args.dist:
+        loads = 0
+        stores = 0
+        atoms = 0
+        totalops = 0
+
     with open(extfile, "r") as f:
         for ln in f:
             ln = ln.strip()
@@ -212,11 +228,13 @@ if __name__ == "__main__":
                     # trying TRAIN clears instead
                     cache.invalidate() # a new test is starting, so 'empty' the cache
                     cache.clear_pLRU()
-                    #numtests +=1
                     if args.verbose:
                         print("New Test")
                         
             else:
+                if args.dist:
+                    totalops += 1
+                
                 if lninfo[1] == 'F':
                     cache.flush()
                     if args.verbose:
@@ -229,13 +247,37 @@ if __name__ == "__main__":
                     addr = int(lninfo[0], 16)
                     iswrite = lninfo[1] == 'W' or lninfo[1] == 'A'
                     result = cache.cacheaccess(addr, iswrite)
+                    
                     if args.verbose:
                         tag, setnum, offset = cache.splitaddr(addr)
                         print(hex(addr), hex(tag), hex(setnum), hex(offset), lninfo[2], result)
+                    
+                    if args.perf:
+                        if result == 'H':
+                            hits += 1
+                        else:
+                            misses += 1
+                    
+                    if args.dist:
+                        if lninfo[1] == 'R':
+                            loads += 1
+                        elif lninfo[1] == 'W':
+                            stores += 1
+                        elif lninfo[1] == 'A':
+                            atoms += 1
+                    
                     if not result == lninfo[2]:
-                        print("Result mismatch at address", lninfo[0], ". Wally:", lninfo[2],", Sim:", result) #, "in test", numtests)
+                        print("Result mismatch at address", lninfo[0]+ ". Wally:", lninfo[2]+", Sim:", result)
-                        
+                        nofails = False
-                        
+    if args.dist:
-
+        percent_loads = str(round(100*loads/totalops))
+        percent_stores = str(round(100*stores/totalops))
+        percent_atoms = str(round(100*atoms/totalops))
+        print("This log had", percent_loads+"% loads,", percent_stores+"% stores, and", percent_atoms+"% atomic operations.")
     
-
+    if args.perf:
+        ratio = round(hits/misses,3)
+        print("There were", hits, "hits and", misses, "misses. The hit/miss ratio was", str(ratio)+".")
+    
+    if nofails:
+        print("SUCCESS! There were no mismatches between Wally and the sim.")

sim/rv64gc_CacheSim.py

@@ -0,0 +1,80 @@
+#!/usr/bin/env python3
+
+###########################################
+## CacheSimTest.py
+##
+## Written: lserafini@hmc.edu
+## Created: 11 April 2023
+## Modified: 12 April 2023
+##
+## Purpose: Run the cache simulator on each rv64gc test suite in turn. 
+##
+## A component of the CORE-V-WALLY configurable RISC-V project.
+##
+## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+##
+## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+##
+## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+## except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+## may obtain a copy of the License at
+##
+## https:##solderpad.org/licenses/SHL-2.1/
+##
+## Unless required by applicable law or agreed to in writing, any work distributed under the 
+## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+## either express or implied. See the License for the specific language governing permissions 
+## and limitations under the License.
+################################################################################################
+import sys
+import os
+import argparse
+
+# NOTE: make sure testbench.sv has the ICache and DCache loggers enabled!
+# This does not check the test output for correctness, run regression for that.
+# Add -p or --perf to report the hit/miss ratio. 
+# Add -d or --dist to report the distribution of loads, stores, and atomic ops.
+# These distributions may not add up to 100; this is because of flushes or invalidations.
+
+class bcolors:
+    HEADER = '\033[95m'
+    OKBLUE = '\033[94m'
+    OKCYAN = '\033[96m'
+    OKGREEN = '\033[92m'
+    WARNING = '\033[93m'
+    FAIL = '\033[91m'
+    ENDC = '\033[0m'
+    BOLD = '\033[1m'
+    UNDERLINE = '\033[4m'
+
+# tests64gc = ["coverage64gc", "arch64f", "arch64d", "arch64i", "arch64priv", "arch64c",  "arch64m", 
+tests64gc = ["coverage64gc", "arch64i", "arch64priv", "arch64c",  "arch64m",             
+             "arch64zi", "wally64a", "wally64periph", "wally64priv", 
+             "arch64zba",  "arch64zbb",  "arch64zbc",  "arch64zbs", 
+             "imperas64f", "imperas64d", "imperas64c", "imperas64i"]
+
+cachetypes = ["ICache", "DCache"]
+simdir = os.path.expanduser("~/cvw/sim")
+
+if __name__ == '__main__':
+    parser = argparse.ArgumentParser(description="Runs the cache simulator on all rv64gc test suites")
+    parser.add_argument('-p', "--perf", action='store_true', help="Report hit/miss ratio")
+    parser.add_argument('-d', "--dist", action='store_true', help="Report distribution of operations")
+
+    args = parser.parse_args()
+
+    testcmd = "vsim -do \"do wally-batch.do rv64gc {}\" -c > /dev/null"
+    cachecmd = "CacheSim.py 64 4 56 44 -f {}"
+    
+    if args.perf:
+        cachecmd += " -p"
+    if args.dist:
+        cachecmd += " -d"
+    
+    for test in tests64gc:
+        print(f"{bcolors.HEADER}Commencing test", test+f":{bcolors.ENDC}")
+        os.system(testcmd.format(test))
+        for cache in cachetypes:
+            print(f"{bcolors.OKCYAN}Running the", cache, f"simulator.{bcolors.ENDC}")
+            os.system(cachecmd.format(cache+".log"))
+        print()

src/cache/cache.sv

@@ -129,7 +129,7 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
   // Select victim way for associative caches
   if(NUMWAYS > 1) begin:vict
     cacheLRU #(NUMWAYS, SETLEN, OFFSETLEN, NUMLINES) cacheLRU(
-      .clk, .reset, .CacheEn, .HitWay, .ValidWay, .VictimWay, .CacheSet, .LRUWriteEn(LRUWriteEn & ~FlushStage),
+      .clk, .reset, .CacheEn, .FlushStage, .HitWay, .ValidWay, .VictimWay, .CacheSet, .LRUWriteEn,
       .SetValid, .PAdr(PAdr[SETTOP-1:OFFSETLEN]), .InvalidateCache, .FlushCache);
   end else 
     assign VictimWay = 1'b1; // one hot.

testbench/testbench.sv

@@ -557,31 +557,38 @@ end
 
   if (`ICACHE_SUPPORTED && `I_CACHE_ADDR_LOGGER) begin : ICacheLogger
     int    file;
-	string LogFile;
+    string LogFile;
-	logic  resetD, resetEdge;
+    logic  resetD, resetEdge;
     logic  Enable;
     // assign Enable = ~dut.core.StallD & ~dut.core.FlushD & dut.core.ifu.bus.icache.CacheRWF[1] & ~reset;
     
     // this version of Enable allows for accurate eviction logging.
     // Likely needs further improvement.
-    assign Enable = dut.core.ifu.bus.icache.icache.cachefsm.LRUWriteEn & ~reset;
+    assign Enable = dut.core.ifu.bus.icache.icache.cachefsm.LRUWriteEn & 
-	flop #(1) ResetDReg(clk, reset, resetD);
+                    dut.core.ifu.immu.immu.pmachecker.Cacheable &
-	assign resetEdge = ~reset & resetD;
+                    ~dut.core.ifu.bus.icache.icache.cachefsm.FlushStage &
+                    ~reset;
+	  flop #(1) ResetDReg(clk, reset, resetD);
+	  assign resetEdge = ~reset & resetD;
+
+    flop #(1) InvalReg(clk, dut.core.ifu.InvalidateICacheM, InvalDelayed);
+	  assign InvalEdge = dut.core.ifu.InvalidateICacheM & ~InvalDelayed;
+
     initial begin
-	  LogFile = $psprintf("ICache.log");
+	    LogFile = $psprintf("ICache.log");
       file = $fopen(LogFile, "w");
-	  $fwrite(file, "BEGIN %s\n", memfilename);
+	    $fwrite(file, "BEGIN %s\n", memfilename);
-	end
+	  end
     string AccessTypeString, HitMissString;
     assign HitMissString = dut.core.ifu.bus.icache.icache.CacheHit ? "H" :
                            dut.core.ifu.bus.icache.icache.vict.cacheLRU.AllValid ? "E" : "M";
-    assign AccessTypeString = dut.core.ifu.InvalidateICacheM ? "I" : "R";
     always @(posedge clk) begin
 	  if(resetEdge) $fwrite(file, "TRAIN\n");
 	  if(Begin) $fwrite(file, "BEGIN %s\n", memfilename);
 	  if(Enable) begin  // only log i cache reads
-	    $fwrite(file, "%h %s %s\n", dut.core.ifu.PCPF, AccessTypeString, HitMissString);
+	    $fwrite(file, "%h R %s\n", dut.core.ifu.PCPF, HitMissString);
 	  end
+    if(InvalEdge) $fwrite(file, "0 I X\n");
 	  if(EndSample) $fwrite(file, "END %s\n", memfilename);
     end
   end
@@ -612,6 +619,7 @@ end
     // Likely needs further improvement.
     assign Enabled = dut.core.lsu.bus.dcache.dcache.cachefsm.LRUWriteEn &
                      ~dut.core.lsu.bus.dcache.dcache.cachefsm.FlushStage &
+                     dut.core.lsu.dmmu.dmmu.pmachecker.Cacheable &
                      (AccessTypeString != "NULL");
 
     initial begin
@@ -625,6 +633,7 @@ end
 	  if(Enabled) begin
 	    $fwrite(file, "%h %s %s\n", dut.core.lsu.PAdrM, AccessTypeString, HitMissString);
 	  end
+    if(dut.core.lsu.bus.dcache.dcache.cachefsm.FlushFlag) $fwrite(file, "0 F X\n");
 	  if(EndSample) $fwrite(file, "END %s\n", memfilename);
     end
   end