Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

More FP unpacking fix

Browse Source
This commit is contained in:
David Harris 2022-01-06 22:22:22 +00:00
parent 340752616d
commit 1c96b22b8f
2 changed files with 6 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
pipelined/src/fpu/unpacking.sv
View File

@ -26,12 +26,12 @@ module unpacking (
logic [31:0] XFloat, YFloat, ZFloat; // Bottom half or NaN, if RV64 and not properly NaN boxed logic [31:0] XFloat, YFloat, ZFloat; // Bottom half or NaN, if RV64 and not properly NaN boxed
// Determine if number is NaN as double precision to check single precision NaN boxing // Determine if number is NaN as double precision to check single precision NaN boxing
if (`FLEN==32) begin if (`XLEN==32) begin // eventually this should change to FLEN when RV32f has FLEN=32
assign XFloat = X[31:0]; assign XFloat = X[31:0];
assign XFloat = Y[31:0]; assign YFloat = Y[31:0];
assign XFloat = Z[31:0]; assign ZFloat = Z[31:0];
end else begin end else begin
assign XFloat = &X[`FLEN-1:32] ? X[31:0] : 32'h7fc00000; assign XFloat = &X[`FLEN-1:32] ? X[31:0] : 32'h7fc00000;
assign YFloat = &Y[`FLEN-1:32] ? Y[31:0] : 32'h7fc00000; assign YFloat = &Y[`FLEN-1:32] ? Y[31:0] : 32'h7fc00000;
assign ZFloat = &Z[`FLEN-1:32] ? Z[31:0] : 32'h7fc00000; assign ZFloat = &Z[`FLEN-1:32] ? Z[31:0] : 32'h7fc00000;
end end

3
pipelined/testbench/tests.vh
View File

@ -240,6 +240,7 @@ string imperas32f[] = '{
string imperas64f[] = '{ string imperas64f[] = '{
`IMPERASTEST, `IMPERASTEST,
"rv64i_m/F/FMUL-S-DYN-RDN-01", "002010", // ***extra
"rv64i_m/F/FADD-S-DYN-RDN-01", "002010", "rv64i_m/F/FADD-S-DYN-RDN-01", "002010",
"rv64i_m/F/FADD-S-DYN-RMM-01", "002010", "rv64i_m/F/FADD-S-DYN-RMM-01", "002010",
"rv64i_m/F/FADD-S-DYN-RNE-01", "002010", "rv64i_m/F/FADD-S-DYN-RNE-01", "002010",
@ -1354,7 +1355,7 @@ string imperas32f[] = '{
"rv32i_m/F/fnmsub_b17-01", "39d0", "rv32i_m/F/fnmsub_b17-01", "39d0",
"rv32i_m/F/fnmsub_b18-01", "4d10", "rv32i_m/F/fnmsub_b18-01", "4d10",
"rv32i_m/F/fnmsub_b2-01", "4d60", "rv32i_m/F/fnmsub_b2-01", "4d60",
"rv32i_m/F/fnmsub_b3-01", "4df0", // inputs that don't exist in memfile //"rv32i_m/F/fnmsub_b3-01", "4df0", // inputs that don't exist in memfile
"rv32i_m/F/fnmsub_b4-01", "3700", "rv32i_m/F/fnmsub_b4-01", "3700",
"rv32i_m/F/fnmsub_b5-01", "3ac0", "rv32i_m/F/fnmsub_b5-01", "3ac0",
"rv32i_m/F/fnmsub_b6-01", "3700", "rv32i_m/F/fnmsub_b6-01", "3700",