From 1c6ebb86a313aaae24ce9b09090cdfbc7d0dd9d3 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 20 Jun 2024 12:54:12 -0700 Subject: [PATCH] Added some debug code to count frames sent to the ethernet mac and frames sent to the phy. Removed the external reset of the phy and now it always reliably starts in the same way. The first 0x117 frames are always captured. --- fpga/rvvidaemon/rvvidaemon.c | 2 +- fpga/src/fpgaTopArtyA7.sv | 5 +++-- src/rvvi/packetizer.sv | 10 +++++++--- testbench/testbench.sv | 9 ++++++++- 4 files changed, 19 insertions(+), 7 deletions(-) diff --git a/fpga/rvvidaemon/rvvidaemon.c b/fpga/rvvidaemon/rvvidaemon.c index 074ffa21c..8a714dee0 100644 --- a/fpga/rvvidaemon/rvvidaemon.c +++ b/fpga/rvvidaemon/rvvidaemon.c @@ -213,8 +213,8 @@ int main(int argc, char **argv){ DecodeRVVI(buf + headerbytes, payloadbytes, &InstructionData); // now let's drive IDV // start simple just drive and compare PC. - ProcessRvviAll(&InstructionData); PrintInstructionData(&InstructionData); + ProcessRvviAll(&InstructionData); } } diff --git a/fpga/src/fpgaTopArtyA7.sv b/fpga/src/fpgaTopArtyA7.sv index 51de188db..f495e2568 100644 --- a/fpga/src/fpgaTopArtyA7.sv +++ b/fpga/src/fpgaTopArtyA7.sv @@ -1134,7 +1134,7 @@ module fpgaTop packetizer #(P, MAX_CSRS) packetizer(.rvvi, .valid, .m_axi_aclk(CPUCLK), .m_axi_aresetn(~bus_struct_reset), .RVVIStall, .RvviAxiWdata, .RvviAxiWstrb, .RvviAxiWlast, .RvviAxiWvalid, .RvviAxiWready); - eth_mac_mii_fifo #(.TARGET("GENERIC"), .CLOCK_INPUT_STYLE("BUFG"), .AXIS_DATA_WIDTH(32), .TX_FIFO_DEPTH(1024)) ethernet(.rst(bus_struct_reset), .logic_clk(CPUCLK), .logic_rst(bus_struct_reset), + eth_mac_mii_fifo #(.TARGET("XILINX"), .CLOCK_INPUT_STYLE("BUFG"), .AXIS_DATA_WIDTH(32), .TX_FIFO_DEPTH(1024)) ethernet(.rst(bus_struct_reset), .logic_clk(CPUCLK), .logic_rst(bus_struct_reset), .tx_axis_tdata(RvviAxiWdata), .tx_axis_tkeep(RvviAxiWstrb), .tx_axis_tvalid(RvviAxiWvalid), .tx_axis_tready(RvviAxiWready), .tx_axis_tlast(RvviAxiWlast), .tx_axis_tuser('0), .rx_axis_tdata(), .rx_axis_tkeep(), .rx_axis_tvalid(), .rx_axis_tready(1'b1), .rx_axis_tlast(), .rx_axis_tuser(), @@ -1155,7 +1155,8 @@ module fpgaTop .cfg_ifg(8'd12), .cfg_tx_enable(1'b1), .cfg_rx_enable(1'b1) ); - assign phy_reset_n = ~bus_struct_reset; + //assign phy_reset_n = ~bus_struct_reset; + assign phy_reset_n = ~1'b0; endmodule diff --git a/src/rvvi/packetizer.sv b/src/rvvi/packetizer.sv index 8ccec184d..e12e9cd7e 100644 --- a/src/rvvi/packetizer.sv +++ b/src/rvvi/packetizer.sv @@ -62,7 +62,8 @@ module packetizer import cvw::*; #(parameter cvw_t P, typedef enum {STATE_RST, STATE_COUNT, STATE_RDY, STATE_WAIT, STATE_TRANS, STATE_TRANS_INSERT_DELAY} statetype; (* mark_debug = "true" *) statetype CurrState, NextState; - logic [31:0] RstCount; + logic [31:0] RstCount; +(* mark_debug = "true" *) logic [31:0] FrameCount; logic RstCountRst, RstCountEn, CountFlag, DelayFlag; @@ -101,8 +102,11 @@ module packetizer import cvw::*; #(parameter cvw_t P, counter #(32) rstcounter(m_axi_aclk, RstCountRst, RstCountEn, RstCount); assign CountFlag = RstCount == 32'd100000000; //assign CountFlag = RstCount == 32'd10; - //assign DelayFlag = RstCount == 32'd200; - assign DelayFlag = RstCount == 32'd0; + assign DelayFlag = RstCount == 32'd200; + //assign DelayFlag = RstCount == 32'd0; + + counter #(32) framecounter(m_axi_aclk, ~m_axi_aresetn, (RvviAxiWready & RvviAxiWlast), FrameCount); + flopenr #(187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12)) rvvireg(m_axi_aclk, ~m_axi_aresetn, valid, rvvi, rvviDelay); diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 399a5453d..098280423 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -633,7 +633,14 @@ module testbench; .rx_error_bad_fcs, .rx_fifo_overflow, .rx_fifo_bad_frame, .rx_fifo_good_frame, .cfg_ifg(8'd12), .cfg_tx_enable(1'b1), .cfg_rx_enable(1'b1) ); - + + logic MiiTxEnDelay; + logic EthernetTXCounterEn; + logic [31:0] EthernetTXCount; + flopr #(1) txedgereg(clk, reset, mii_tx_en, MiiTxEnDelay); + assign EthernetTXCounterEn = ~mii_tx_en & MiiTxEnDelay; + counter #(32) ethernexttxcounter(clk, reset, EthernetTXCounterEn, EthernetTXCount); + end else begin assign RVVIStall = '0; end