diff --git a/pipelined/src/ppa/ppa.sv b/pipelined/src/ppa/ppa.sv index 01e06bb71..03b004f69 100644 --- a/pipelined/src/ppa/ppa.sv +++ b/pipelined/src/ppa/ppa.sv @@ -3,6 +3,14 @@ // & mmasserfrye@hmc.edu // Measure PPA of various building blocks +module ppa_comparator_8 #(parameter WIDTH=8) ( + input logic [WIDTH-1:0] a, b, + input logic sgnd, + output logic [1:0] flags); + + ppa_comparator #(WIDTH) comp (.*); +endmodule + module ppa_comparator_16 #(parameter WIDTH=16) ( input logic [WIDTH-1:0] a, b, input logic sgnd, @@ -27,6 +35,14 @@ module ppa_comparator_64 #(parameter WIDTH=64) ( ppa_comparator #(WIDTH) comp (.*); endmodule +module ppa_comparator_128 #(parameter WIDTH=128) ( + input logic [WIDTH-1:0] a, b, + input logic sgnd, + output logic [1:0] flags); + + ppa_comparator #(WIDTH) comp (.*); +endmodule + module ppa_comparator #(parameter WIDTH=16) ( input logic [WIDTH-1:0] a, b, input logic sgnd, @@ -45,6 +61,13 @@ module ppa_comparator #(parameter WIDTH=16) ( assign flags = {eq, lt}; endmodule +module ppa_add_8 #(parameter WIDTH=8) ( + input logic [WIDTH-1:0] a, b, + output logic [WIDTH-1:0] y); + + assign y = a + b; +endmodule + module ppa_add_16 #(parameter WIDTH=16) ( input logic [WIDTH-1:0] a, b, output logic [WIDTH-1:0] y); @@ -66,6 +89,19 @@ module ppa_add_64 #(parameter WIDTH=64) ( assign y = a + b; endmodule +module ppa_add_128 #(parameter WIDTH=128) ( + input logic [WIDTH-1:0] a, b, + output logic [WIDTH-1:0] y); + + assign y = a + b; +endmodule + +module ppa_mult_8 #(parameter WIDTH=8) ( + input logic [WIDTH-1:0] a, b, + output logic [WIDTH*2-1:0] y); //is this right width + assign y = a * b; +endmodule + module ppa_mult_16 #(parameter WIDTH=16) ( input logic [WIDTH-1:0] a, b, output logic [WIDTH*2-1:0] y); //is this right width @@ -84,6 +120,12 @@ module ppa_mult_64 #(parameter WIDTH=64) ( assign y = a * b; endmodule +module ppa_mult_128 #(parameter WIDTH=128) ( + input logic [WIDTH-1:0] a, b, + output logic [WIDTH*2-1:0] y); //is this right width + assign y = a * b; +endmodule + module ppa_alu_16 #(parameter WIDTH=16) ( input logic [WIDTH-1:0] A, B, input logic [2:0] ALUControl, @@ -180,6 +222,15 @@ module ppa_shiftleft #(parameter WIDTH=32) ( assign y = a << amt; endmodule +module ppa_shifter_8 #(parameter WIDTH=8) ( + input logic [WIDTH-1:0] A, + input logic [$clog2(WIDTH)-1:0] Amt, + input logic Right, Arith, W64, + output logic [WIDTH-1:0] Y); + + ppa_shifter #(WIDTH) sh (.*); +endmodule + module ppa_shifter_16 #(parameter WIDTH=16) ( input logic [WIDTH-1:0] A, input logic [$clog2(WIDTH)-1:0] Amt, @@ -207,6 +258,15 @@ module ppa_shifter_64 #(parameter WIDTH=64) ( ppa_shifter #(WIDTH) sh (.*); endmodule +module ppa_shifter_128 #(parameter WIDTH=128) ( + input logic [WIDTH-1:0] A, + input logic [$clog2(WIDTH)-1:0] Amt, + input logic Right, Arith, W64, + output logic [WIDTH-1:0] Y); + + ppa_shifter #(WIDTH) sh (.*); +endmodule + module ppa_shifter #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, input logic [$clog2(WIDTH)-1:0] Amt, @@ -221,14 +281,7 @@ module ppa_shifter #(parameter WIDTH=32) ( // For RV64, 32 and 64-bit shifts are needed, with sign extension. // funnel shifter input (see CMOS VLSI Design 4e Section 11.8.1, note Table 11.11 shift types wrong) - if (WIDTH==32) begin:shifter // RV32 - always_comb // funnel mux - if (Right) - if (Arith) z = {{31{A[31]}}, A}; - else z = {31'b0, A}; - else z = {A, 31'b0}; - assign amttrunc = Amt; // shift amount - end else begin:shifter // RV64 + if (WIDTH == 64) begin:shifter // RV64 fix what about 128 always_comb // funnel mux if (W64) begin // 32-bit shifts if (Right) @@ -241,8 +294,15 @@ module ppa_shifter #(parameter WIDTH=32) ( else z = {63'b0, A}; else z = {A, 63'b0}; end - assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32 or 64-bit shift - end + end else begin:shifter // RV32, + always_comb // funnel mux + if (Right) + if (Arith) z = {{WIDTH-1{A[WIDTH-1]}}, A}; + else z = {{WIDTH-1{1'b0}}, A}; + else z = {A, {WIDTH-1{1'b0}}}; + assign amttrunc = Amt; // shift amount + end + assign amttrunc = (W64 & WIDTH==64) ? {1'b0, Amt[4:0]} : Amt; // 32 or 64-bit shift fix // opposite offset for right shfits assign offset = Right ? amttrunc : ~amttrunc; diff --git a/pipelined/srt/Makefile b/pipelined/srt/Makefile index db5a11f86..73a0b75fa 100644 --- a/pipelined/srt/Makefile +++ b/pipelined/srt/Makefile @@ -3,5 +3,5 @@ all: sqrttestgen testgen sqrttestgen: sqrttestgen.c gcc sqrttestgen.c -lm -o sqrttestgen -testgen: exptestgen.c - gcc exptestgen.c -lm -o exptestgen +testgen: testgen.c + gcc testgen.c -lm -o testgen diff --git a/pipelined/srt/lint-srt b/pipelined/srt/lint-srt index 3599cdff5..399201be0 100755 --- a/pipelined/srt/lint-srt +++ b/pipelined/srt/lint-srt @@ -1,2 +1 @@ verilator --lint-only --top-module srt srt.sv -I../config/rv64gc -I../config/shared ../src/generic/*.sv ../src/generic/flop/*.sv -verilator --lint-only --top-module testbench testbench.sv -I../config/rv64gc -I../config/shared ../src/generic/*.sv ../src/generic/flop/*.sv ../src/fpu/unpack.sv diff --git a/pipelined/srt/srt.do b/pipelined/srt/srt.do index b4d9bb138..8be358057 100644 --- a/pipelined/srt/srt.do +++ b/pipelined/srt/srt.do @@ -17,7 +17,7 @@ if [file exists work] { } vlib work -vlog +incdir+../config/rv64gc +incdir+../config/shared srt.sv testbench.sv ../src/generic/flop/flop*.sv ../src/generic/mux.sv ../src/fpu/unpack.sv +vlog +incdir+../config/rv64gc +incdir+../config/shared srt.sv testbench.sv ../src/generic/flop/flop*.sv ../src/generic/mux.sv vopt +acc work.testbench -o workopt vsim workopt diff --git a/pipelined/srt/srt.sv b/pipelined/srt/srt.sv index 81d9e2f25..044bac9c1 100644 --- a/pipelined/srt/srt.sv +++ b/pipelined/srt/srt.sv @@ -37,8 +37,6 @@ module srt #(parameter Nf=52) ( input logic Flush, // *** multiple pipe stages // Floating Point Inputs // later add exponents, signs, special cases - input logic [10:0] SrcXExpE, SrcYExpE, // exponents, for double precision exponents are 11 bits - // end of floating point inputs input logic [Nf-1:0] SrcXFrac, SrcYFrac, input logic [`XLEN-1:0] SrcA, SrcB, input logic [1:0] Fmt, // Floats: 00 = 16 bit, 01 = 32 bit, 10 = 64 bit, 11 = 128 bit @@ -47,7 +45,6 @@ module srt #(parameter Nf=52) ( input logic Int, // Choose integer inputss input logic Sqrt, // perform square root, not divide output logic [Nf-1:0] Quot, Rem, // *** later handle integers - output logic [10:0] Exp, // output exponent is hardcoded for 11 bits for double precision output logic [3:0] Flags ); @@ -81,9 +78,6 @@ module srt #(parameter Nf=52) ( // Partial Product Generation csa csa(WS, WC, Dsel, qp, WSA, WCA); - // Exponent division - exp exp(SrcXExpE, SrcYExpE, Exp); - srtpostproc postproc(rp, rm, Quot); endmodule @@ -92,9 +86,8 @@ module srtpostproc #(parameter N=52) ( output [N-1:0] Quot ); - // replace with on-the-fly conversion //assign Quot = rp - rm; - finaladd finaladd(rp, rm, Quot); + finaladd finaladd(rp, rm, Quot); endmodule module srtpreproc #(parameter Nf=52) ( @@ -254,14 +247,6 @@ module csa #(parameter N=56) ( (in2[54:0] & in3[54:0]), cin}; endmodule -////////////// -// exponent // -////////////// -module exp(input [10:0] e1, e2, - output [10:0] e); // for double precision, exponent is 11 bits - assign e = (e1 - e2) + 11'd1023; // bias is hardcoded -endmodule - ////////////// // finaladd // ////////////// diff --git a/pipelined/srt/srt_stanford.sv b/pipelined/srt/srt_stanford.sv index 23ab683d5..ce0417f56 100644 --- a/pipelined/srt/srt_stanford.sv +++ b/pipelined/srt/srt_stanford.sv @@ -11,9 +11,7 @@ // This Verilog file models a radix 2 SRT divider which // produces one quotient digit per cycle. The divider // keeps the partial remainder in carry-save form. - -`include "wally-config.vh" - + ///////// // srt // ///////// @@ -328,9 +326,7 @@ module testbench; begin req <= #5 1; $display("result was %h, should be %h\n", r, correctr); - //if (abs(correctr - r) > 1) // check if accurate to 1 ulp - // giving error "srt_stanford.sv(395): (vopt-7063) Failed to find 'abs' in hierarchical name 'abs'." - if (correctr - r > 1) // check if accurate to 1 ulp + if ((correctr - r) > 1) // check if accurate to 1 ulp begin errors = errors+1; $display("failed\n"); diff --git a/pipelined/srt/testbench.sv b/pipelined/srt/testbench.sv index 9985a89cf..0af3821ec 100644 --- a/pipelined/srt/testbench.sv +++ b/pipelined/srt/testbench.sv @@ -1,7 +1,7 @@ ///////////// -// divcounter // +// counter // ///////////// -module divcounter(input logic clk, +module counter(input logic clk, input logic req, output logic done); @@ -36,76 +36,40 @@ endmodule ////////// // testbench // ////////// - -/* verilator lint_off STMTDLY */ -/* verilator lint_off INFINITELOOP */ module testbench; logic clk; logic req; logic done; - logic [63:0] a; - logic [63:0] b; - logic [63:0] result; - logic [51:0] r; + logic [51:0] a; + logic [51:0] b; + logic [51:0] r; logic [54:0] rp, rm; // positive quotient digits - logic [10:0] e; // output exponent - // input logic for Unpacker - // input logic [63:0] X, Y, Z, - numbers - // input logic FmtE, ---- format, 1 is for double precision, 0 is single - // input logic [2:0] FOpCtrlE, ---- controling operations for FPU, 1 is sqrt, 0 is divide - // all variables are commented in fpu.sv - - // output logic from Unpacker - logic XSgnE, YSgnE, ZSgnE; - logic [10:0] XExpE, YExpE, ZExpE; // exponent - logic [52:0] XManE, YManE, ZManE; - logic XNormE; - logic XNaNE, YNaNE, ZNaNE; - logic XSNaNE, YSNaNE, ZSNaNE; - logic XDenormE, YDenormE, ZDenormE; // denormals - logic XZeroE, YZeroE, ZZeroE; - logic [10:0] BiasE; // currrently hardcoded, will probs be removed - logic XInfE, YInfE, ZInfE; - logic XExpMaxE; // says exponent is all ones, can ignore - // Test parameters - parameter MEM_SIZE = 60000; - parameter MEM_WIDTH = 64+64+64; + parameter MEM_SIZE = 40000; + parameter MEM_WIDTH = 52+52+52; - `define memr 63:0 - `define memb 127:64 - `define mema 191:128 + `define memr 51:0 + `define memb 103:52 + `define mema 155:104 // Test logicisters logic [MEM_WIDTH-1:0] Tests [0:MEM_SIZE]; // Space for input file logic [MEM_WIDTH-1:0] Vec; // Verilog doesn't allow direct access to a // bit field of an array - logic [63:0] correctr, nextr, diffn, diffp; + logic [51:0] correctr, nextr, diffn, diffp; integer testnum, errors; - // Unpacker - // Note: BiasE will probably get taken out eventually - unpack unpack(.X({1'b1,a[62:0]}), .Y({1'b1,b[62:0]}), .Z(64'b0), .FmtE(1'b1), - .XSgnE(XSgnE), .YSgnE(YSgnE), .ZSgnE(ZSgnE), .XExpE(XExpE), .YExpE(YExpE), .ZExpE(ZExpE), - .XManE(XManE), .YManE(YManE), .ZManE(ZManE), .XNormE(XNormE), .XNaNE(XNaNE), .YNaNE(YNaNE), .ZNaNE(ZNaNE), - .XSNaNE(XSNaNE), .YSNaNE(YSNaNE), .ZSNaNE(ZSNaNE), .XDenormE(XDenormE), .YDenormE(YDenormE), .ZDenormE(ZDenormE), - .XZeroE(XZeroE), .YZeroE(YZeroE), .ZZeroE(ZZeroE), - .XInfE(XInfE), .YInfE(YInfE), .ZInfE(ZInfE), .XExpMaxE(XExpMaxE)); - // Divider srt #(52) srt(.clk, .Start(req), .Stall(1'b0), .Flush(1'b0), - .SrcXExpE(XExpE), .SrcYExpE(YExpE), - .SrcXFrac(XManE[51:0]), .SrcYFrac(YManE[51:0]), + .SrcXFrac(a), .SrcYFrac(b), .SrcA('0), .SrcB('0), .Fmt(2'b00), .W64(1'b0), .Signed(1'b0), .Int(1'b0), .Sqrt(1'b0), - .Quot(r), .Rem(), .Exp(e), .Flags()); + .Quot(r), .Rem(), .Flags()); - assign result = {1'b0, e, r}; - - // Divcounter - divcounter divcounter(clk, req, done); + // Counter + counter counter(clk, req, done); initial @@ -126,7 +90,7 @@ module testbench; a = Vec[`mema]; b = Vec[`memb]; nextr = Vec[`memr]; - req = #5 1; + req <= #5 1; end // Apply directed test vectors read from file. @@ -135,19 +99,17 @@ module testbench; begin if (done) begin - req = #5 1; - diffp = correctr - result; - diffn = result - correctr; + req <= #5 1; + diffp = correctr - r; + diffn = r - correctr; if (($signed(diffn) > 1) | ($signed(diffp) > 1)) // check if accurate to 1 ulp begin errors = errors+1; - $display("a = %h b = %h result = %h",a,b,correctr); - $display("result was %h, should be %h %h %h\n", result, correctr, diffn, diffp); - $display("at fail"); + $display("result was %h, should be %h %h %h\n", r, correctr, diffn, diffp); $display("failed\n"); $stop; end - if (a === 64'hxxxxxxxxxxxxxxxx) + if (a === 52'hxxxxxxxxxxxxx) begin $display("%d Tests completed successfully", testnum); $stop; @@ -155,20 +117,16 @@ module testbench; end if (req) begin - req = #5 0; + req <= #5 0; correctr = nextr; - $display("pre increment"); testnum = testnum+1; - a = Vec[`mema]; - b = Vec[`memb]; Vec = Tests[testnum]; - $display("a = %h b = %h result = %h",a,b,nextr); + $display("a = %h b = %h",a,b); + a = Vec[`mema]; + b = Vec[`memb]; nextr = Vec[`memr]; - $display("after increment"); end end endmodule -/* verilator lint_on STMTDLY */ -/* verilator lint_on INFINITELOOP */ diff --git a/pipelined/srt/testgen.c b/pipelined/srt/testgen.c index 143ef058f..98d52819b 100644 --- a/pipelined/srt/testgen.c +++ b/pipelined/srt/testgen.c @@ -28,7 +28,7 @@ double random_input(void); void main(void) { FILE *fptr; - double x1, x2, a, b, r; + double a, b, r; double list[ENTRIES] = {1, 1.5, 1.25, 1.125, 1.0625, 1.75, 1.875, 1.99999, 1.1, 1.2, 1.01, 1.001, 1.0001, @@ -63,7 +63,6 @@ void main(void) void output(FILE *fptr, double a, double b, double r) { - printhex(fptr, a); fprintf(fptr, "_"); printhex(fptr, b); diff --git a/pipelined/srt/testvectors b/pipelined/srt/testvectors index c6412a9e6..112803fe9 100644 --- a/pipelined/srt/testvectors +++ b/pipelined/srt/testvectors @@ -1,289 +1,789 @@ -4000000000000000_4000000000000000_3ff0000000000000 -4018000000000000_4000000000000000_4008000000000000 -4024000000000000_4000000000000000_4014000000000000 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+388a7114e229c_5202a405480a9_d96b8ce030793 +5112a225444a8_71c8e391c7239_d2b5183c88cc1 +2b485690ad216_ba017402e805d_5aad01f0f330a +0130026004c01_e1edc3db87b71_113c45ac1389f +abf757eeafdd6_7a9af535ea6bd_21604b0e84524 +350c6a18d431a_82c905920b242_9918ede81ed1a +2a8c5518aa315_8cbf197e32fc6_8146816fcd820 +80b3016602cc0_915922b245648_eac2cca581d9f diff --git a/synthDC/Synopsys_stack_trace_12580.txt b/synthDC/Synopsys_stack_trace_12580.txt new file mode 100644 index 000000000..ca9522e03 --- /dev/null +++ b/synthDC/Synopsys_stack_trace_12580.txt @@ -0,0 +1,17 @@ +GNU gdb (GDB) Red Hat Enterprise Linux 8.2-16.el8 +Copyright (C) 2018 Free Software Foundation, Inc. +License GPLv3+: GNU GPL version 3 or later +This is free software: you are free to change and redistribute it. +There is NO WARRANTY, to the extent permitted by law. +Type "show copying" and "show warranty" for details. +This GDB was configured as "x86_64-redhat-linux-gnu". +Type "show configuration" for configuration details. +For bug reporting instructions, please see: +. +Find the GDB manual and other documentation resources online at: + . + +For help, type "help". +Type "apropos word" to search for commands related to "word". +Attaching to process 12580 +(gdb) (gdb) (gdb) (gdb) \ No newline at end of file diff --git a/synthDC/Synopsys_stack_trace_32764.txt b/synthDC/Synopsys_stack_trace_32764.txt new file mode 100644 index 000000000..f845fa3f8 --- /dev/null +++ b/synthDC/Synopsys_stack_trace_32764.txt @@ -0,0 +1,17 @@ +GNU gdb (GDB) Red Hat Enterprise Linux 8.2-16.el8 +Copyright (C) 2018 Free Software Foundation, Inc. +License GPLv3+: GNU GPL version 3 or later +This is free software: you are free to change and redistribute it. +There is NO WARRANTY, to the extent permitted by law. +Type "show copying" and "show warranty" for details. +This GDB was configured as "x86_64-redhat-linux-gnu". +Type "show configuration" for configuration details. +For bug reporting instructions, please see: +. +Find the GDB manual and other documentation resources online at: + . + +For help, type "help". +Type "apropos word" to search for commands related to "word". +Attaching to process 32764 +(gdb) (gdb) (gdb) (gdb) \ No newline at end of file diff --git a/synthDC/Synopsys_stack_trace_57184.txt b/synthDC/Synopsys_stack_trace_57184.txt new file mode 100644 index 000000000..a016d47c4 --- /dev/null +++ b/synthDC/Synopsys_stack_trace_57184.txt @@ -0,0 +1,17 @@ +GNU gdb (GDB) Red Hat Enterprise Linux 8.2-16.el8 +Copyright (C) 2018 Free Software Foundation, Inc. +License GPLv3+: GNU GPL version 3 or later +This is free software: you are free to change and redistribute it. +There is NO WARRANTY, to the extent permitted by law. +Type "show copying" and "show warranty" for details. +This GDB was configured as "x86_64-redhat-linux-gnu". +Type "show configuration" for configuration details. +For bug reporting instructions, please see: +. +Find the GDB manual and other documentation resources online at: + . + +For help, type "help". +Type "apropos word" to search for commands related to "word". +Attaching to process 57184 +(gdb) (gdb) (gdb) (gdb) \ No newline at end of file diff --git a/synthDC/Synopsys_stack_trace_57185.txt b/synthDC/Synopsys_stack_trace_57185.txt new file mode 100644 index 000000000..dec54674a --- /dev/null +++ b/synthDC/Synopsys_stack_trace_57185.txt @@ -0,0 +1,17 @@ +GNU gdb (GDB) Red Hat Enterprise Linux 8.2-16.el8 +Copyright (C) 2018 Free Software Foundation, Inc. +License GPLv3+: GNU GPL version 3 or later +This is free software: you are free to change and redistribute it. +There is NO WARRANTY, to the extent permitted by law. +Type "show copying" and "show warranty" for details. +This GDB was configured as "x86_64-redhat-linux-gnu". +Type "show configuration" for configuration details. +For bug reporting instructions, please see: +. +Find the GDB manual and other documentation resources online at: + . + +For help, type "help". +Type "apropos word" to search for commands related to "word". +Attaching to process 57185 +(gdb) (gdb) (gdb) (gdb) \ No newline at end of file diff --git a/synthDC/crte_000012580.txt b/synthDC/crte_000012580.txt new file mode 100644 index 000000000..2bc74daac --- /dev/null +++ b/synthDC/crte_000012580.txt @@ -0,0 +1,67 @@ +CRTE_SNAPSHOT_START + +SECTION_CRTE_VERSION +3.0 + +SECTION_PID +12580 + +SECTION_POLLING_INTERVAL +5 + +SECTION_DATE_TIME +Mon May 16 23:44:09 UTC 2022 (1652744649) + +SECTION_OS_VERSION +osname: Linux +hostname: tera +arch: x86_64 +release_version: 5.4.157-1-pve + +SECTION_IPC_INFO + +------ Message Queues -------- +key msqid owner perms used-bytes messages + +------ Shared Memory Segments -------- +key shmid owner perms bytes nattch status +0x00000000 15859713 nwhyte-agu 600 524288 2 dest +0x00000000 360451 nwhyte-agu 600 524288 2 dest +0x00000000 65540 kkim 600 134217728 2 dest +0x00000000 557061 nwhyte-agu 600 67108864 2 dest +0x00000000 6 harris 600 524288 2 dest +0x00000000 7 harris 600 524288 2 dest +0x00000000 5275656 harris 600 2097152 2 dest +0x00000000 11993097 kkim 600 524288 2 dest +0x00000000 15892490 kkim 600 524288 2 dest +0x00000000 11 harris 600 524288 2 SECTION_ULIMIT +core file size (blocks, -c) 0 +data seg size (kbytes, -d) unlimited +scheduling priority (-e) 0 +file size (blocks, -f) unlimited +pending signals (-i) 515072 +max locked memory (kbytes, -l) 64 +max memory size (kbytes, -m) unlimited +open files (-n) 524288 +pipe size (512 bytes, -p) 8 +POSIX message queues (bytes, -q) 819200 +real-time priority (-r) 0 +stack size (kbytes, -s) unlimited +cpu time (seconds, -t) unlimited +max user processes (-u) 515072 +virtual memory (kbytes, -v) unlimited +file locks (-x) unlimited + +SECTION_SYSCONF +_SC_THREAD_SAFE_FUNCTIONS= 200809 +_SC_CLK_TCK= 100 +_SC_OPEN_MAX= 524288 +_SC_PAGE_SIZE= 4096 +_SC_ARG_MAX= 4611686018427387903 +_SC_CHILD_MAX= 515072 +_SC_LINE_MAX= 2048 + +SECTION_FULL_COMMAND +/cad/synopsys/SYN/linux64/syn/bin/common_shell_exec -64 -shell dc_shell -r /cad/synopsys/SYN -f scripts/synth.tcl + +SECTION_CPUINFO diff --git a/synthDC/crte_000032764.txt b/synthDC/crte_000032764.txt new file mode 100644 index 000000000..87eaa3c4c --- /dev/null +++ b/synthDC/crte_000032764.txt @@ -0,0 +1,67 @@ +CRTE_SNAPSHOT_START + +SECTION_CRTE_VERSION +3.0 + +SECTION_PID +32764 + +SECTION_POLLING_INTERVAL +5 + +SECTION_DATE_TIME +Tue May 17 00:05:18 UTC 2022 (1652745918) + +SECTION_OS_VERSION +osname: Linux +hostname: tera +arch: x86_64 +release_version: 5.4.157-1-pve + +SECTION_IPC_INFO + +------ Message Queues -------- +key msqid owner perms used-bytes messages + +------ Shared Memory Segments -------- +key shmid owner perms bytes nattch status +0x00000000 360451 nwhyte-agu 600 524288 2 dest +0x00000000 65540 kkim 600 134217728 2 dest +0x00000000 557061 nwhyte-agu 600 67108864 2 dest +0x00000000 6 harris 600 524288 2 dest +0x00000000 7 harris 600 524288 2 dest +0x00000000 5275656 harris 600 2097152 2 dest +0x00000000 11993097 kkim 600 524288 2 dest +0x00000000 15892490 kkim 600 524288 2 dest +0x00000000 11 harris 600 524288 2 dest +0x00000000 15204364 harris 644 790528 3 SECTION_ULIMIT +core file size (blocks, -c) 0 +data seg size (kbytes, -d) unlimited +scheduling priority (-e) 0 +file size (blocks, -f) unlimited +pending signals (-i) 515072 +max locked memory (kbytes, -l) 64 +max memory size (kbytes, -m) unlimited +open files (-n) 524288 +pipe size (512 bytes, -p) 8 +POSIX message queues (bytes, -q) 819200 +real-time priority (-r) 0 +stack size (kbytes, -s) unlimited +cpu time (seconds, -t) unlimited +max user processes (-u) 515072 +virtual memory (kbytes, -v) unlimited +file locks (-x) unlimited + +SECTION_SYSCONF +_SC_THREAD_SAFE_FUNCTIONS= 200809 +_SC_CLK_TCK= 100 +_SC_OPEN_MAX= 524288 +_SC_PAGE_SIZE= 4096 +_SC_ARG_MAX= 4611686018427387903 +_SC_CHILD_MAX= 515072 +_SC_LINE_MAX= 2048 + +SECTION_FULL_COMMAND +/cad/synopsys/SYN/linux64/syn/bin/common_shell_exec -64 -shell dc_shell -r /cad/synopsys/SYN -f scripts/synth.tcl + +SECTION_CPUINFO diff --git a/synthDC/crte_000057184.txt b/synthDC/crte_000057184.txt new file mode 100644 index 000000000..77c41bece --- /dev/null +++ b/synthDC/crte_000057184.txt @@ -0,0 +1,67 @@ +CRTE_SNAPSHOT_START + +SECTION_CRTE_VERSION +3.0 + +SECTION_PID +57184 + +SECTION_POLLING_INTERVAL +5 + +SECTION_DATE_TIME +Mon May 16 22:54:26 UTC 2022 (1652741666) + +SECTION_OS_VERSION +osname: Linux +hostname: tera +arch: x86_64 +release_version: 5.4.157-1-pve + +SECTION_IPC_INFO + +------ Message Queues -------- +key msqid owner perms used-bytes messages + +------ Shared Memory Segments -------- +key shmid owner perms bytes nattch status +0x00000000 15859713 nwhyte-agu 600 524288 2 dest +0x00000000 360451 nwhyte-agu 600 524288 2 dest +0x00000000 65540 kkim 600 134217728 2 dest +0x00000000 557061 nwhyte-agu 600 67108864 2 dest +0x00000000 6 harris 600 524288 2 dest +0x00000000 7 harris 600 524288 2 dest +0x00000000 5275656 harris 600 2097152 2 dest +0x00000000 11993097 kkim 600 524288 2 dest +0x00000000 15892490 kkim 600 524288 2 dest +0x00000000 11 harris 600 524288 2 SECTION_ULIMIT +core file size (blocks, -c) 0 +data seg size (kbytes, -d) unlimited +scheduling priority (-e) 0 +file size (blocks, -f) unlimited +pending signals (-i) 515072 +max locked memory (kbytes, -l) 64 +max memory size (kbytes, -m) unlimited +open files (-n) 524288 +pipe size (512 bytes, -p) 8 +POSIX message queues (bytes, -q) 819200 +real-time priority (-r) 0 +stack size (kbytes, -s) unlimited +cpu time (seconds, -t) unlimited +max user processes (-u) 515072 +virtual memory (kbytes, -v) unlimited +file locks (-x) unlimited + +SECTION_SYSCONF +_SC_THREAD_SAFE_FUNCTIONS= 200809 +_SC_CLK_TCK= 100 +_SC_OPEN_MAX= 524288 +_SC_PAGE_SIZE= 4096 +_SC_ARG_MAX= 4611686018427387903 +_SC_CHILD_MAX= 515072 +_SC_LINE_MAX= 2048 + +SECTION_FULL_COMMAND +/cad/synopsys/SYN/linux64/syn/bin/common_shell_exec -64 -shell dc_shell -r /cad/synopsys/SYN -f scripts/synth.tcl + +SECTION_CPUINFO diff --git a/synthDC/crte_000057185.txt b/synthDC/crte_000057185.txt new file mode 100644 index 000000000..d99b82eb3 --- /dev/null +++ b/synthDC/crte_000057185.txt @@ -0,0 +1,67 @@ +CRTE_SNAPSHOT_START + +SECTION_CRTE_VERSION +3.0 + +SECTION_PID +57185 + +SECTION_POLLING_INTERVAL +5 + +SECTION_DATE_TIME +Mon May 16 22:54:26 UTC 2022 (1652741666) + +SECTION_OS_VERSION +osname: Linux +hostname: tera +arch: x86_64 +release_version: 5.4.157-1-pve + +SECTION_IPC_INFO + +------ Message Queues -------- +key msqid owner perms used-bytes messages + +------ Shared Memory Segments -------- +key shmid owner perms bytes nattch status +0x00000000 15859713 nwhyte-agu 600 524288 2 dest +0x00000000 360451 nwhyte-agu 600 524288 2 dest +0x00000000 65540 kkim 600 134217728 2 dest +0x00000000 557061 nwhyte-agu 600 67108864 2 dest +0x00000000 6 harris 600 524288 2 dest +0x00000000 7 harris 600 524288 2 dest +0x00000000 5275656 harris 600 2097152 2 dest +0x00000000 11993097 kkim 600 524288 2 dest +0x00000000 15892490 kkim 600 524288 2 dest +0x00000000 11 harris 600 524288 2 SECTION_ULIMIT +core file size (blocks, -c) 0 +data seg size (kbytes, -d) unlimited +scheduling priority (-e) 0 +file size (blocks, -f) unlimited +pending signals (-i) 515072 +max locked memory (kbytes, -l) 64 +max memory size (kbytes, -m) unlimited +open files (-n) 524288 +pipe size (512 bytes, -p) 8 +POSIX message queues (bytes, -q) 819200 +real-time priority (-r) 0 +stack size (kbytes, -s) unlimited +cpu time (seconds, -t) unlimited +max user processes (-u) 515072 +virtual memory (kbytes, -v) unlimited +file locks (-x) unlimited + +SECTION_SYSCONF +_SC_THREAD_SAFE_FUNCTIONS= 200809 +_SC_CLK_TCK= 100 +_SC_OPEN_MAX= 524288 +_SC_PAGE_SIZE= 4096 +_SC_ARG_MAX= 4611686018427387903 +_SC_CHILD_MAX= 515072 +_SC_LINE_MAX= 2048 + +SECTION_FULL_COMMAND +/cad/synopsys/SYN/linux64/syn/bin/common_shell_exec -64 -shell dc_shell -r /cad/synopsys/SYN -f scripts/synth.tcl + +SECTION_CPUINFO diff --git a/synthDC/ppa.py b/synthDC/ppa.py deleted file mode 100755 index 4d1657771..000000000 --- a/synthDC/ppa.py +++ /dev/null @@ -1,64 +0,0 @@ -#!/usr/bin/python3 -# from msilib.schema import File -import subprocess -from multiprocessing import Pool -import csv -import re -# import matplotlib.pyplot as plt -# import numpy as np - -print("hi") - -def run_command(module, width, freq): - command = "make synth DESIGN=ppa_{}_{} TECH=sky90 DRIVE=INV FREQ={} MAXOPT=1".format(module, width, freq) - subprocess.Popen(command, shell=True) - -widths = ['16'] -modules = ['shifter'] -freqs = ['10'] - - -LoT = [] -for module in modules: - for width in widths: - for freq in freqs: - LoT += [[module, width, freq]] - -pool = Pool() -pool.starmap(run_command, LoT) -pool.close() - -bashCommand = "grep 'Critical Path Length' runs/ppa_*/reports/*qor*" -outputCPL = subprocess.check_output(['bash','-c', bashCommand]) -linesCPL = outputCPL.decode("utf-8").split('\n')[:-1] - -bashCommand = "grep 'Design Area' runs/ppa_*/reports/*qor*" -outputDA = subprocess.check_output(['bash','-c', bashCommand]) -linesDA = outputDA.decode("utf-8").split('\n')[:-1] - -cpl = re.compile('\d{1}\.\d{6}') -f = re.compile('_\d*_MHz') -wm = re.compile('ppa_\w*_\d*_qor') -da = re.compile('\d*\.\d{6}') - -allSynths = [] - -for i in range(len(linesCPL)): - line = linesCPL[i] - oneSynth = [] - mwm = wm.findall(line)[0][4:-4].split('_') - oneSynth += [mwm[0]] - oneSynth += [mwm[1]] - oneSynth += [f.findall(line)[0][1:-4]] - oneSynth += cpl.findall(line) - oneSynth += da.findall(linesDA[i]) - allSynths += [oneSynth] - -file = open("ppaData.csv", "w") -writer = csv.writer(file) -writer.writerow(['Module', 'Width', 'Target Freq', 'Delay', 'Area']) - -for one in allSynths: - writer.writerow(one) - -file.close() \ No newline at end of file diff --git a/synthDC/ppaAnalyze.py b/synthDC/ppaAnalyze.py new file mode 100755 index 000000000..fef78921a --- /dev/null +++ b/synthDC/ppaAnalyze.py @@ -0,0 +1,95 @@ +#!/usr/bin/python3 +import subprocess +import csv +import re +import matplotlib.pyplot as plt +import numpy as np + +def getData(): + bashCommand = "grep 'Critical Path Length' runs/ppa_*/reports/*qor*" + outputCPL = subprocess.check_output(['bash','-c', bashCommand]) + linesCPL = outputCPL.decode("utf-8").split('\n')[:-1] + + bashCommand = "grep 'Design Area' runs/ppa_*/reports/*qor*" + outputDA = subprocess.check_output(['bash','-c', bashCommand]) + linesDA = outputDA.decode("utf-8").split('\n')[:-1] + + cpl = re.compile('\d{1}\.\d{6}') + f = re.compile('_\d*_MHz') + wm = re.compile('ppa_\w*_\d*_qor') + da = re.compile('\d*\.\d{6}') + + allSynths = [] + + for i in range(len(linesCPL)): + line = linesCPL[i] + mwm = wm.findall(line)[0][4:-4].split('_') + oneSynth = [mwm[0], int(mwm[1])] + oneSynth += [int(f.findall(line)[0][1:-4])] + oneSynth += [float(cpl.findall(line)[0])] + oneSynth += [float(da.findall(linesDA[i])[0])] + allSynths += [oneSynth] + + return allSynths + +def writeCSV(allSynths): + file = open("ppaData.csv", "w") + writer = csv.writer(file) + writer.writerow(['Module', 'Width', 'Target Freq', 'Delay', 'Area']) + + for one in allSynths: + writer.writerow(one) + + file.close() + +def plotPPA(module, freq, var): + ''' + module: string module name + freq: int freq (GHz) + var: string 'delay' or 'area' + plots chosen variable vs width for all matching syntheses with regression + ''' + global allSynths + ind = 3 if (var == 'delay') else 4 + widths = [] + ivar = [] + for oneSynth in allSynths: + if (oneSynth[0] == module) & (oneSynth[2] == freq): + + widths += [oneSynth[1]] + ivar += [oneSynth[ind]] + + x = np.array(widths, dtype=np.int) + y = np.array(ivar, dtype=np.float) + + A = np.vstack([x, np.ones(len(x))]).T + m, c = np.linalg.lstsq(A, y, rcond=None)[0] + + z = np.polyfit(x, y, 2) + p = np.poly1d(z) + + zlog = np.polyfit(np.log(x), y, 1) + plog = np.poly1d(zlog) + + xp = np.linspace(0, 140, 200) + xplog = np.log(xp) + + _ = plt.plot(x, y, 'o', label=module, markersize=10) + _ = plt.plot(x, m*x + c, 'r', label='Linear fit') + _ = plt.plot(xp, p(xp), label='Quadratic fit') + _ = plt.plot(xp, plog(xplog), label = 'Log fit') + _ = plt.legend() + _ = plt.xlabel("Width (bits)") + _ = plt.ylabel(str.title(var)) + _ = plt.title("Target frequency " + str(freq)) + plt.show() +#fix square microns, picosec, end plots at 8 to stop negs, add equation to plots and R2 +# try linear term with delay as well (w and wo) + +allSynths = getData() + +writeCSV(allSynths) + +plotPPA('mult', 5000, 'delay') +plotPPA('mult', 5000, 'area') +plotPPA('mult', 10, 'area') \ No newline at end of file diff --git a/synthDC/ppaData.csv b/synthDC/ppaData.csv index 368547c60..d5232bb4e 100644 --- a/synthDC/ppaData.csv +++ b/synthDC/ppaData.csv @@ -1,28 +1,38 @@ Module,Width,Target Freq,Delay,Area +add,128,10,7.100851,1867.879976 +add,128,5000,0.389771,7007.980119 add,16,10,2.032906,221.479998 -add,16,4000,0.249839,551.740010 +add,16,4000,0.249839,551.74001 add,16,5000,0.228259,924.140017 add,16,6000,0.225754,1120.140018 add,32,10,4.160501,456.679995 add,32,4000,0.280842,1730.680031 -add,32,5000,0.250500,1933.540033 -add,32,6000,0.271774,1746.360030 +add,32,5000,0.2505,1933.540033 +add,32,6000,0.271774,1746.36003 add,64,10,8.474034,927.079988 add,64,4000,0.323267,3758.300065 add,64,5000,0.334061,3798.480071 add,64,6000,0.328457,3749.480066 +add,8,10,0.940062,103.879999 +add,8,5000,0.199689,197.960003 +comparator,128,10,0.842074,1997.240039 +comparator,128,5000,0.260142,5215.56005 comparator,16,10,0.576329,252.840005 comparator,16,4000,0.249312,280.280005 comparator,16,5000,0.199026,313.600006 comparator,16,6000,0.166568,422.380007 -comparator,32,10,0.765874,495.880010 -comparator,32,4000,0.249950,608.580012 +comparator,32,10,0.765874,495.88001 +comparator,32,4000,0.24995,608.580012 comparator,32,5000,0.205372,919.240014 -comparator,32,6000,0.201200,1248.520016 -comparator,64,10,0.561562,1008.420020 +comparator,32,6000,0.2012,1248.520016 +comparator,64,10,0.561562,1008.42002 comparator,64,4000,0.249905,1437.660027 comparator,64,5000,0.219296,2738.120023 comparator,64,6000,0.221138,2341.220025 +comparator,8,10,0.29577,118.580002 +comparator,8,5000,0.195502,129.360003 +mult,128,10,9.334627,180734.540854 +mult,128,5000,1.78322,314617.244472 mult,16,10,4.730546,3869.040009 mult,16,4000,0.821111,9132.620147 mult,16,5000,0.820059,9583.420143 @@ -31,11 +41,16 @@ mult,32,10,7.575772,12412.680067 mult,32,4000,1.091389,31262.980534 mult,32,5000,1.092153,31497.200524 mult,32,6000,1.084816,33519.920555 -mult,64,10,4.793300,46798.920227 +mult,64,10,4.7933,46798.920227 mult,64,4000,1.411752,93087.261425 mult,64,5000,1.404875,94040.801492 mult,64,6000,1.415466,89931.661403 -shifter,16,10,0.000000,0.000000 +mult,8,10,2.076433,1009.399998 +mult,8,5000,0.552339,4261.040075 +shifter,128,10,2.577935,8113.420158 +shifter,128,5000,0.395847,16602.180268 +shifter,16,10,0.0,0.0 +shifter,16,10,0.0,0.0 shifter,32,10,1.906335,1656.200032 shifter,32,10,1.906335,1656.200032 shifter,32,10,1.906335,1656.200032 @@ -48,3 +63,5 @@ shifter,32,5000,0.238962,4985.260077 shifter,32,6000,0.241742,4312.000069 shifter,32,6000,0.241742,4312.000069 shifter,32,6000,0.241742,4312.000069 +shifter,8,10,0.0,0.0 +shifter,8,5000,0.0,0.0 diff --git a/synthDC/ppaSynth.py b/synthDC/ppaSynth.py new file mode 100755 index 000000000..654d77391 --- /dev/null +++ b/synthDC/ppaSynth.py @@ -0,0 +1,37 @@ +#!/usr/bin/python3 +import subprocess +from multiprocessing import Pool + + +def runCommand(module, width, tech, freq): + command = "make synth DESIGN=ppa_{}_{} TECH={} DRIVE=INV FREQ={} MAXOPT=1".format(module, width, tech, freq) + subprocess.Popen(command, shell=True) + +def deleteRedundant(LoT): + '''removes any previous runs for the current synthesis specifications''' + synthStr = "rm -rf runs/ppa_{}_{}_rv32e_{}nm_{}_*" + for synth in LoT: + bashCommand = synthStr.format(*synth) + outputCPL = subprocess.check_output(['bash','-c', bashCommand]) + +widths = ['128'] +modules = ['mult'] +freqs = ['5000'] +tech = 'sky90' + +#to run: add 8 10, shifter 8 16 (check .sv!) + +LoT = [] +for module in modules: + for width in widths: + for freq in freqs: + LoT += [[module, width, tech, freq]] + +deleteRedundant(LoT) + +pool = Pool() +pool.starmap(runCommand, LoT) +pool.close() + +bashCommand = "wait" +outputCPL = subprocess.check_output(['bash','-c', bashCommand]) \ No newline at end of file diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index 9d6aac68a..368e45f3a 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -137,6 +137,10 @@ if {$tech == "sky130"} { # Set the wire load model set_wire_load_mode "top" +# Set switching activities +# default activity factors are 1 for clocks, 0.1 for others +# static probability of 0.5 is used for leakage + # Attempt Area Recovery - if looking for minimal area # set_max_area 2000 @@ -359,4 +363,4 @@ redirect $filename { report_constraint } set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_hier.rep"] # redirect $filename { report_hierarchy } -quit +#quit