diff --git a/pipelined/src/cache/AHBBuscachefsm.sv b/pipelined/src/cache/AHBBuscachefsm.sv index 0101e8f16..7645ab1df 100644 --- a/pipelined/src/cache/AHBBuscachefsm.sv +++ b/pipelined/src/cache/AHBBuscachefsm.sv @@ -74,15 +74,14 @@ module AHBBuscachefsm #(parameter integer WordCountThreshold, logic [LOGWPL-1:0] NextWordCount; logic WordCountFlag; logic [2:0] LocalBurstType; - logic CntReset; + logic WordCntReset; logic [1:0] RWDelay, CacheRWDelay; - assign CntReset = BusNextState == STATE_READY; // Used to send address for address stage of AHB. flopenr #(LOGWPL) WordCountReg(.clk(HCLK), - .reset(~HRESETn | CntReset), + .reset(~HRESETn | WordCntReset), .en(WordCntEn), .d(NextWordCount), .q(WordCount)); @@ -90,7 +89,7 @@ module AHBBuscachefsm #(parameter integer WordCountThreshold, // Used to store data from data phase of AHB. flopenr #(LOGWPL) WordCountDelayedReg(.clk(HCLK), - .reset(~HRESETn | CntReset), + .reset(~HRESETn | WordCntReset), .en(WordCntEn), .d(WordCount), .q(WordCountDelayed)); @@ -99,6 +98,7 @@ module AHBBuscachefsm #(parameter integer WordCountThreshold, assign WordCountFlag = (WordCountDelayed == WordCountThreshold[LOGWPL-1:0] ); // Detect when we are waiting on the final access. assign WordCntEn = (BusNextState == STATE_CACHE_ACCESS & HREADY) | (BusNextState == STATE_READY & |CacheRW & HREADY); + assign WordCntReset = BusNextState == STATE_READY; // replace with fsm with two more states. flopenr #(2) RWReg(HCLK, ~HRESETn, 1'b1, RW, RWDelay); diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 32ee36e21..a511d6162 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -37,16 +37,12 @@ module ifu ( input logic FlushF, FlushD, FlushE, FlushM, // Bus interface (* mark_debug = "true" *) input logic [`XLEN-1:0] HRDATA, -(* mark_debug = "true" *) input logic IFUBusAck, -(* mark_debug = "true" *) input logic IFUBusInit, (* mark_debug = "true" *) output logic [`PA_BITS-1:0] IFUHADDR, -(* mark_debug = "true" *) output logic IFUBusRead, (* mark_debug = "true" *) output logic IFUStallF, (* mark_debug = "true" *) output logic [2:0] IFUHBURST, (* mark_debug = "true" *) output logic [1:0] IFUHTRANS, (* mark_debug = "true" *) output logic IFUHWRITE, (* mark_debug = "true" *) input logic IFUHREADY, -(* mark_debug = "true" *) output logic IFUTransComplete, (* mark_debug = "true" *) output logic [`XLEN-1:0] PCF, // Execute output logic [`XLEN-1:0] PCLinkE, @@ -250,24 +246,16 @@ module ifu ( flopen #(`XLEN) fb(.clk, .en(CaptureEn), .d(HRDATA), .q(AllInstrRawF[31:0])); -/* -----\/----- EXCLUDED -----\/----- - busfsm #(LOGBWPL) busfsm( - .clk, .reset, .RW(NonIROMMemRWM & ~{ITLBMissF, ITLBMissF}), - .BusAck(IFUBusAck), .BusInit(IFUBusInit), .CPUBusy, - .BusStall, .BusWrite(), .BusRead(IFUBusRead), - .HTRANS(IFUHTRANS), .BusCommitted()); - -----/\----- EXCLUDED -----/\----- */ AHBBusfsm busfsm(.HCLK(clk), .HRESETn(~reset), .RW(NonIROMMemRWM & ~{ITLBMissF, ITLBMissF}), .CaptureEn, .BusCommitted(), .CPUBusy, .HREADY(IFUHREADY), .BusStall, .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE)); assign IFUHBURST = 3'b0; - assign IFUTransComplete = IFUBusAck; assign {ICacheFetchLine, ICacheStallF, FinalInstrRawF} = '0; assign {ICacheMiss, ICacheAccess} = '0; end end else begin : nobus // block: bus - assign {BusStall, IFUBusRead} = '0; + assign BusStall = '0; assign {ICacheStallF, ICacheMiss, ICacheAccess} = '0; assign AllInstrRawF = FinalInstrRawF; end diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 70fbd8fc0..41b602b6c 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -72,10 +72,6 @@ module lsu ( output logic StoreAmoMisalignedFaultM, StoreAmoAccessFaultM, // connect to ahb (* mark_debug = "true" *) output logic [`PA_BITS-1:0] LSUHADDR, - (* mark_debug = "true" *) output logic LSUBusRead, - (* mark_debug = "true" *) output logic LSUBusWrite, - (* mark_debug = "true" *) input logic LSUBusAck, - (* mark_debug = "true" *) input logic LSUBusInit, (* mark_debug = "true" *) input logic [`XLEN-1:0] HRDATA, (* mark_debug = "true" *) output logic [`XLEN-1:0] LSUHWDATA, (* mark_debug = "true" *) input logic LSUHREADY, @@ -84,7 +80,6 @@ module lsu ( (* mark_debug = "true" *) output logic [2:0] LSUHBURST, (* mark_debug = "true" *) output logic [1:0] LSUHTRANS, (* mark_debug = "true" *) output logic [`XLEN/8-1:0] LSUHWSTRB, - (* mark_debug = "true" *) output logic LSUTransComplete, // page table walker input logic [`XLEN-1:0] SATP_REGW, // from csr input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, @@ -278,6 +273,7 @@ module lsu ( flop #(`XLEN) wdreg(clk, LSUHWDATA_noDELAY, LSUHWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN // *** bummer need a second byte mask for bus as it is XLEN rather than LLEN. + // probably can merge by muxing LSUPAdrM's LLEN/8-1 index bit based on HTRANS being != 0. logic [`XLEN/8-1:0] BusByteMaskM; swbytemask #(`XLEN) busswbytemask(.Size(LSUHSIZE), .Adr(LSUPAdrM[$clog2(`XLEN/8)-1:0]), .ByteMask(BusByteMaskM)); @@ -294,21 +290,12 @@ module lsu ( flop #(`XLEN) wdreg(clk, LSUWriteDataM, LSUHWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN flop #(`XLEN/8) HWSTRBReg(clk, ByteMaskM, LSUHWSTRB); -/* -----\/----- EXCLUDED -----\/----- - busfsm #(LOGBWPL) busfsm( - .clk, .reset, .RW(LSURWM & ~{IgnoreRequest, IgnoreRequest}), - .BusAck(LSUBusAck), .BusInit(LSUBusInit), .CPUBusy, - .BusStall, .BusWrite(LSUBusWrite), .BusRead(LSUBusRead), - .HTRANS(LSUHTRANS), .BusCommitted(BusCommittedM)); - -----/\----- EXCLUDED -----/\----- */ - AHBBusfsm busfsm(.HCLK(clk), .HRESETn(~reset), .RW(LSURWM & ~{IgnoreRequest, IgnoreRequest}), .BusCommitted(BusCommittedM), .CPUBusy, .BusStall, .CaptureEn, .HREADY(LSUHREADY), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE)); assign ReadDataWordMuxM = LittleEndianReadDataWordM; // from byte swapping assign LSUHBURST = 3'b0; - assign LSUTransComplete = LSUBusAck; assign {DCacheStallM, DCacheCommittedM, DCacheMiss, DCacheAccess} = '0; end end else begin: nobus // block: bus diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index 4d6ec36db..95ff25ecc 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -133,19 +133,13 @@ module wallypipelinedcore ( // AHB ifu interface logic [`PA_BITS-1:0] IFUHADDR; - logic IFUBusRead; - logic IFUBusAck, IFUBusInit; logic [2:0] IFUHBURST; logic [1:0] IFUHTRANS; - logic IFUTransComplete; logic IFUHWRITE; logic IFUHREADY; // AHB LSU interface logic [`PA_BITS-1:0] LSUHADDR; - logic LSUBusRead; - logic LSUBusWrite; - logic LSUBusAck, LSUBusInit; logic [`XLEN-1:0] LSUHWDATA; logic [`XLEN/8-1:0] LSUHWSTRB; logic LSUHWRITE; @@ -161,7 +155,6 @@ module wallypipelinedcore ( logic [2:0] LSUHSIZE; logic [2:0] LSUHBURST; logic [1:0] LSUHTRANS; - logic LSUTransComplete; logic DCacheMiss; logic DCacheAccess; @@ -178,8 +171,8 @@ module wallypipelinedcore ( .StallF, .StallD, .StallE, .StallM, .FlushF, .FlushD, .FlushE, .FlushM, // Fetch - .HRDATA, .IFUBusAck, .IFUBusInit, .PCF, .IFUHADDR, - .IFUBusRead, .IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUTransComplete, + .HRDATA, .PCF, .IFUHADDR, + .IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUHREADY, .IFUHWRITE, .ICacheAccess, .ICacheMiss, @@ -264,8 +257,8 @@ module wallypipelinedcore ( .IEUAdrE, .IEUAdrM, .WriteDataM, .ReadDataW, .FlushDCacheM, // connected to ahb (all stay the same) - .LSUHADDR, .LSUBusRead, .LSUBusWrite, .LSUBusAck, .LSUBusInit, - .HRDATA, .LSUHWDATA, .LSUHWSTRB, .LSUHSIZE, .LSUHBURST, .LSUHTRANS, .LSUTransComplete, + .LSUHADDR, + .HRDATA, .LSUHWDATA, .LSUHWSTRB, .LSUHSIZE, .LSUHBURST, .LSUHTRANS, .LSUHWRITE, .LSUHREADY, // connect to csr or privilege and stay the same. @@ -295,43 +288,14 @@ module wallypipelinedcore ( // *** Ross: please make EBU conditional when only supporting internal memories if(`BUS) begin : ebu -/* -----\/----- EXCLUDED -----\/----- - ahblite ebu(// IFU connections - .clk, .reset, - .UnsignedLoadM(1'b0), .AtomicMaskedM(2'b00), - .IFUHADDR, .IFUBusRead, - .IFUHBURST, - .IFUHTRANS, - .IFUTransComplete, - .IFUBusAck, - .IFUBusInit, - .IFUHWRITE, - .IFUHREADY, - - // Signals from Data Cache - .LSUHADDR, .LSUBusRead, .LSUBusWrite, .LSUHWDATA, - .LSUHSIZE, - .LSUHBURST, - .LSUHTRANS, - .LSUTransComplete, - .LSUBusAck, - .LSUBusInit, - .LSUHWRITE, - .LSUHREADY, - - .HREADY, .HRESP, .HCLK, .HRESETn, - .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, - .HPROT, .HTRANS, .HMASTLOCK); - -----/\----- EXCLUDED -----/\----- */ - ahbmultimanager ebu(// IFU connections .clk, .reset, + // IFU interface .IFUHADDR, .IFUHBURST, .IFUHTRANS, .IFUHREADY, - - // Signals from Data Cache + // LSU interface .LSUHADDR, .LSUHWDATA, .LSUHWSTRB, @@ -340,7 +304,7 @@ module wallypipelinedcore ( .LSUHTRANS, .LSUHWRITE, .LSUHREADY, - + // BUS interface .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK);