From 9c70ab917c36ab007f67c07c6de01fe3c2ec4d5c Mon Sep 17 00:00:00 2001 From: cturek Date: Sun, 13 Nov 2022 22:40:26 +0000 Subject: [PATCH 1/6] Added A Date: Sun, 13 Nov 2022 23:02:43 +0000 Subject: [PATCH 2/6] Added flops for n and m, added B=0 signal --- pipelined/src/fpu/fdivsqrt/fdivsqrt.sv | 8 ++++---- .../src/fpu/fdivsqrt/fdivsqrtpostproc.sv | 4 ++-- pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv | 20 +++++++++++-------- 3 files changed, 18 insertions(+), 14 deletions(-) diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv index f5cf2e3f0..2362b9870 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv @@ -64,13 +64,13 @@ module fdivsqrt( logic Firstun; logic WZero; logic SpecialCaseM; - logic [`DIVBLEN:0] n, p, m, L; - logic OTFCSwap, ALTB; + logic [`DIVBLEN:0] n, m; + logic OTFCSwap, ALTB, BZero; fdivsqrtpreproc fdivsqrtpreproc( .clk, .DivStartE, .Xm(XmE), .QeM, .Xe(XeE), .Fmt(FmtE), .Ye(YeE), .Sqrt(SqrtE), .Ym(YmE), .XZero(XZeroE), .X, .Dpreproc, - .n, .p, .m, .L, .OTFCSwap, .ALTB, + .n, .m, .OTFCSwap, .ALTB, .BZero, .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .MDUE, .W64E); fdivsqrtfsm fdivsqrtfsm( .clk, .reset, .FmtE, .XsE, .SqrtE, @@ -85,6 +85,6 @@ module fdivsqrt( fdivsqrtpostproc fdivsqrtpostproc( .WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .Firstun, .SqrtM, .SpecialCaseM, .RemOp(Funct3E[1]), - .MDUE, .n, .ALTB, .m, + .MDUE, .n, .ALTB, .m, .BZero, .QmM, .WZero, .DivSM); endmodule \ No newline at end of file diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv index 44c7f901b..716f12257 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv @@ -38,7 +38,7 @@ module fdivsqrtpostproc( input logic Firstun, input logic SqrtM, input logic SpecialCaseM, - input logic RemOp, MDUE, ALTB, + input logic RemOp, MDUE, ALTB, BZero, input logic [`DIVBLEN:0] n, m, output logic [`DIVb:0] QmM, output logic WZero, @@ -70,7 +70,7 @@ module fdivsqrtpostproc( end assign DivSM = ~WZero & ~(SpecialCaseM & SqrtM); // ***unsure why SpecialCaseM has to be gated by SqrtM, but otherwise fails regression on divide - + // Determine if sticky bit is negative assign W = WC + WS; diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv index 0ee67019d..3d2f529a6 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv @@ -41,8 +41,8 @@ module fdivsqrtpreproc ( input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B input logic [2:0] Funct3E, Funct3M, input logic MDUE, W64E, - output logic [`DIVBLEN:0] n, p, m, L, - output logic OTFCSwap, ALTB, + output logic [`DIVBLEN:0] n, m, + output logic OTFCSwap, ALTB, BZero, output logic [`NE+1:0] QeM, output logic [`DIVb+3:0] X, output logic [`DIVN-2:0] Dpreproc @@ -58,8 +58,9 @@ module fdivsqrtpreproc ( logic [`XLEN-1:0] PosA, PosB; logic As, Bs, OTFCSwapTemp; logic [`XLEN-1:0] A64, B64; + logic [`DIVBLEN:0] Calcn, Calcm; logic [`DIVBLEN:0] ZeroDiff, IntBits, RightShiftX; - logic [`DIVBLEN:0] pPlusr, pPrCeil; + logic [`DIVBLEN:0] pPlusr, pPrCeil, p, L; logic [`LOGRK-1:0] pPrTrunc; logic [`DIVb+3:0] PreShiftX; @@ -75,23 +76,24 @@ module fdivsqrtpreproc ( assign PosA = As ? -A64 : A64; assign PosB = Bs ? -B64 : B64; + assign BZero = |ForwardedSrcBE; assign ZeroBufX = MDUE ? {PosA, {`DIVb-`XLEN{1'b0}}} : {Xm, {`DIVb-`NF-1{1'b0}}}; assign ZeroBufY = MDUE ? {PosB, {`DIVb-`XLEN{1'b0}}} : {Ym, {`DIVb-`NF-1{1'b0}}}; lzc #(`DIVb) lzcX (ZeroBufX, L); - lzc #(`DIVb) lzcY (ZeroBufY, m); + lzc #(`DIVb) lzcY (ZeroBufY, Calcm); assign PreprocX = Xm[`NF-1:0]<> `LOGRK) + {{`DIVBLEN-1{1'b0}}, |(pPrTrunc)}; - assign n = (pPrCeil << `LOGK) - 1; + assign Calcn = (pPrCeil << `LOGK) - 1; assign IntBits = (`DIVBLEN)'(`RK) + p; assign RightShiftX = (`DIVBLEN)'(`RK) - {{(`DIVBLEN-`RK){1'b0}}, IntBits[`RK-1:0]}; @@ -115,7 +117,9 @@ module fdivsqrtpreproc ( // DIVRESLEN/(r*`DIVCOPIES) flopen #(`NE+2) expflop(clk, DivStartE, Qe, QeM); flopen #(1) swapflop(clk, DivStartE, OTFCSwapTemp, OTFCSwap); - expcalc expcalc(.Fmt, .Xe, .Ye, .Sqrt, .XZero, .L, .m, .Qe); + flopen #(`DIVBLEN+1) nflop(clk, DivStartE, Calcn, n); + flopen #(`DIVBLEN+1) mflop(clk, DivStartE, Calcm, m); + expcalc expcalc(.Fmt, .Xe, .Ye, .Sqrt, .XZero, .L, .m(Calcm), .Qe); endmodule From 74f58b5d895f0ca5e87e1a6d841d9af3f90e30a1 Mon Sep 17 00:00:00 2001 From: cturek Date: Sun, 13 Nov 2022 23:44:34 +0000 Subject: [PATCH 3/6] Added Quotient/Remainder calcs to normal termination --- pipelined/src/fpu/fdivsqrt/fdivsqrt.sv | 6 ++-- .../src/fpu/fdivsqrt/fdivsqrtpostproc.sv | 32 ++++++++++++++++--- pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv | 4 +-- 3 files changed, 33 insertions(+), 9 deletions(-) diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv index 2362b9870..14e7cfa99 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv @@ -65,12 +65,12 @@ module fdivsqrt( logic WZero; logic SpecialCaseM; logic [`DIVBLEN:0] n, m; - logic OTFCSwap, ALTB, BZero; + logic OTFCSwap, ALTB, BZero, As; fdivsqrtpreproc fdivsqrtpreproc( .clk, .DivStartE, .Xm(XmE), .QeM, .Xe(XeE), .Fmt(FmtE), .Ye(YeE), .Sqrt(SqrtE), .Ym(YmE), .XZero(XZeroE), .X, .Dpreproc, - .n, .m, .OTFCSwap, .ALTB, .BZero, + .n, .m, .OTFCSwap, .ALTB, .BZero, .As, .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .MDUE, .W64E); fdivsqrtfsm fdivsqrtfsm( .clk, .reset, .FmtE, .XsE, .SqrtE, @@ -85,6 +85,6 @@ module fdivsqrt( fdivsqrtpostproc fdivsqrtpostproc( .WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .Firstun, .SqrtM, .SpecialCaseM, .RemOp(Funct3E[1]), - .MDUE, .n, .ALTB, .m, .BZero, + .MDUE, .n, .ALTB, .m, .BZero, .As, .QmM, .WZero, .DivSM); endmodule \ No newline at end of file diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv index 716f12257..65b68883b 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv @@ -38,16 +38,16 @@ module fdivsqrtpostproc( input logic Firstun, input logic SqrtM, input logic SpecialCaseM, - input logic RemOp, MDUE, ALTB, BZero, + input logic RemOp, MDUE, ALTB, BZero, As, input logic [`DIVBLEN:0] n, m, output logic [`DIVb:0] QmM, output logic WZero, output logic DivSM ); - logic [`DIVb+3:0] W; + logic [`DIVb+3:0] W, Sum; logic [`DIVb:0] PreQmM; - logic NegSticky; + logic NegSticky, PostInc; logic weq0; logic [`DIVb:0] IntQuot, IntRem; @@ -73,9 +73,33 @@ module fdivsqrtpostproc( // Determine if sticky bit is negative - assign W = WC + WS; + assign Sum = WC + WS; + assign W = $signed(Sum) >>> `LOGR; assign NegSticky = W[`DIVb+3]; + assign RemD = {4'b0000, D, {(`DIVb-`DIVN){1'b0}}}; + always_comb + if (~As) + if (NegSticky) begin + assign IntQuot = FirstUM; + assign IntRem = W + RemD; + assign PostInc = 0; + end else begin + assign IntQuot = FirstU; + assign IntRem = W; + assign PostInc = 0; + end + else + if (NegSticky | weq0) begin + assign IntQuot = FirstU; + assign IntRem = W; + assign PostInc = 0; + end else begin + assign IntQuot = FirstU; + assign IntRem = W - RemD; + assign PostInc = 1; + end + // division takes the result from the next cycle, which is shifted to the left one more time so the square root also needs to be shifted assign PreQmM = NegSticky ? FirstUM : FirstU; // Select U or U-1 depending on negative sticky bit diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv index 3d2f529a6..af6a86179 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv @@ -42,7 +42,7 @@ module fdivsqrtpreproc ( input logic [2:0] Funct3E, Funct3M, input logic MDUE, W64E, output logic [`DIVBLEN:0] n, m, - output logic OTFCSwap, ALTB, BZero, + output logic OTFCSwap, ALTB, BZero, As, output logic [`NE+1:0] QeM, output logic [`DIVb+3:0] X, output logic [`DIVN-2:0] Dpreproc @@ -56,7 +56,7 @@ module fdivsqrtpreproc ( // Intdiv signals logic [`DIVb-1:0] ZeroBufX, ZeroBufY; logic [`XLEN-1:0] PosA, PosB; - logic As, Bs, OTFCSwapTemp; + logic Bs, OTFCSwapTemp; logic [`XLEN-1:0] A64, B64; logic [`DIVBLEN:0] Calcn, Calcm; logic [`DIVBLEN:0] ZeroDiff, IntBits, RightShiftX; From 0b2c8b9d460932525b6484de1e48b57837aa7f75 Mon Sep 17 00:00:00 2001 From: cturek Date: Mon, 14 Nov 2022 00:06:38 +0000 Subject: [PATCH 4/6] Added majority of combinational logic --- .../src/fpu/fdivsqrt/fdivsqrtpostproc.sv | 57 +++++++++++++++---- 1 file changed, 46 insertions(+), 11 deletions(-) diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv index 65b68883b..8f2087643 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv @@ -49,7 +49,9 @@ module fdivsqrtpostproc( logic [`DIVb:0] PreQmM; logic NegSticky, PostInc; logic weq0; - logic [`DIVb:0] IntQuot, IntRem; + logic [`DIVBLEN:0] NormShift; + logic [`DIVb:0] IntQuot, IntRem, NormQuot, NormRem; + logic [`DIVb:0] PreResult, Result; // check for early termination on an exact result. If the result is not exact, the sticky should be set aplusbeq0 #(`DIVb+4) wspluswceq0(WS, WC, weq0); @@ -70,8 +72,6 @@ module fdivsqrtpostproc( end assign DivSM = ~WZero & ~(SpecialCaseM & SqrtM); // ***unsure why SpecialCaseM has to be gated by SqrtM, but otherwise fails regression on divide - - // Determine if sticky bit is negative assign Sum = WC + WS; assign W = $signed(Sum) >>> `LOGR; @@ -81,27 +81,62 @@ module fdivsqrtpostproc( always_comb if (~As) if (NegSticky) begin - assign IntQuot = FirstUM; - assign IntRem = W + RemD; + assign NormQuot = FirstUM; + assign NormRem = W + RemD; assign PostInc = 0; end else begin - assign IntQuot = FirstU; - assign IntRem = W; + assign NormQuot = FirstU; + assign NormRem = W; assign PostInc = 0; end else if (NegSticky | weq0) begin - assign IntQuot = FirstU; - assign IntRem = W; + assign NormQuot = FirstU; + assign NormRem = W; assign PostInc = 0; end else begin - assign IntQuot = FirstU; - assign IntRem = W - RemD; + assign NormQuot = FirstU; + assign NormRem = W - RemD; assign PostInc = 1; end + +/* + always_comb + if(ALTB) begin + assign IntQuot = '0; + assign IntRem = ForwardedSrcAE; + end else if (BZero) begin + assign IntQuot = '1; + assign IntRem = ForwardedSrcAE; + end else if (EarlyTerm) begin + if (weq0) begin + assign IntQuot = FirstU; + assign IntRem = '0; + end else begin + assign IntQuot = FirstUM; + assign IntRem = '0; + end + end else begin + assign IntQuot = NormQuot; + assign IntRem = NormRem; + end + */ + /* + always_comb + if (RemOp) begin + assign NormShift = m + (`DIVBLEN)'(`DIVa); + assign PreResult = IntRem; + end else begin + assign NormShift = DIVb - (j << `LOGR); + assign PreResult = IntQuot; + end + */ + // division takes the result from the next cycle, which is shifted to the left one more time so the square root also needs to be shifted + assign Result = ($signed(PreResult) >>> NormShift) + (PostInc & ~RemOp); + assign PreQmM = NegSticky ? FirstUM : FirstU; // Select U or U-1 depending on negative sticky bit assign QmM = SqrtM ? (PreQmM << 1) : PreQmM; endmodule \ No newline at end of file From 79d416537a101137e4c9255f3e50dd91fe402c0b Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 14 Nov 2022 09:52:21 -0800 Subject: [PATCH 5/6] Removed comment about nonexistent possible bug --- pipelined/src/mmu/hptw.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/mmu/hptw.sv b/pipelined/src/mmu/hptw.sv index 746c7d58b..69fc07b15 100644 --- a/pipelined/src/mmu/hptw.sv +++ b/pipelined/src/mmu/hptw.sv @@ -224,7 +224,7 @@ module hptw ( if (`XLEN == 32) begin assign InitialWalkerState = L1_ADR; assign MegapageMisaligned = |(CurrentPPN[9:0]); // must have zero PPN0 - // *** Possible bug - should be L1_ADR? + // *** Possible bug - should be L1_ADR? If so, applies to 64 bits as well assign Misaligned = ((WalkerState == L0_ADR) & MegapageMisaligned); end else begin logic GigapageMisaligned, TerapageMisaligned; From 895ee3d773ee8d70c16b1d8ef4d1f0b7d3a57ba5 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 14 Nov 2022 09:56:33 -0800 Subject: [PATCH 6/6] Removed comment about nonexistent possible bug --- pipelined/src/mmu/hptw.sv | 1 - 1 file changed, 1 deletion(-) diff --git a/pipelined/src/mmu/hptw.sv b/pipelined/src/mmu/hptw.sv index 46f7806a7..bcbefae5a 100644 --- a/pipelined/src/mmu/hptw.sv +++ b/pipelined/src/mmu/hptw.sv @@ -223,7 +223,6 @@ module hptw ( if (`XLEN == 32) begin assign InitialWalkerState = L1_ADR; assign MegapageMisaligned = |(CurrentPPN[9:0]); // must have zero PPN0 - // *** Possible bug - should be L1_ADR? If so, applies to 64 bits as well assign Misaligned = ((WalkerState == L0_ADR) & MegapageMisaligned); end else begin logic GigapageMisaligned, TerapageMisaligned;