diff --git a/wally-pipelined/src/cache/sram1rw.sv b/wally-pipelined/src/cache/sram1rw.sv
index a74593881..2b2c2d60b 100644
--- a/wally-pipelined/src/cache/sram1rw.sv
+++ b/wally-pipelined/src/cache/sram1rw.sv
@@ -15,7 +15,7 @@ module sram1rw #(parameter DEPTH=128, WIDTH=256) (
     always_ff @(posedge clk) begin
         ReadData <= StoredData[Addr];
         if (WriteEnable) begin
-            StoredData[Addr] <= WriteData;
+            StoredData[Addr] <= #1 WriteData;
         end
     end
 endmodule