diff --git a/wally-pipelined/src/clint.sv b/wally-pipelined/src/clint.sv
index e7f520fbc..5db89d7b1 100644
--- a/wally-pipelined/src/clint.sv
+++ b/wally-pipelined/src/clint.sv
@@ -67,6 +67,7 @@ module clint (
         if (reset) begin
           MSIP <= 0;
           MTIME <= 0;
+          MTIMECMP <= 0;
           // MTIMECMP is not reset
         end else if (memwrite) begin
           if (entry == 16'h0000) MSIP <= MaskedWriteDataM[0];
@@ -90,6 +91,7 @@ module clint (
         if (reset) begin
           MSIP <= 0;
           MTIME <= 0;
+          MTIMECMP <= 0;
           // MTIMECMP is not reset
         end else if (memwrite) begin
           if (entry == 16'h0000) MSIP <= MaskedWriteDataM[0];
diff --git a/wally-pipelined/src/ieu.sv b/wally-pipelined/src/ieu.sv
index 147504cb5..d91fd99b2 100644
--- a/wally-pipelined/src/ieu.sv
+++ b/wally-pipelined/src/ieu.sv
@@ -56,7 +56,6 @@ module ieu (
   logic [2:0]  FlagsE;
   logic [4:0]  ALUControlE;
   logic        ALUSrcAE, ALUSrcBE;
-  logic        IllegalInstrFaultM;
   logic [2:0]  Funct3M;
   logic [1:0]  ResultSrcW;