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Renamed DCU to DMEM

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This commit is contained in:
David Harris 2021-02-01 18:52:22 -05:00
parent 5cf3d188c6
commit 1a3963bed0
2 changed files with 5 additions and 5 deletions
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8
wally-pipelined/src/dcu/dcu.sv → wally-pipelined/src/dmem/dmem.sv
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@ -1,12 +1,12 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// dcu.sv // dmem.sv
// //
// Written: David_Harris@hmc.edu 9 January 2021 // Written: David_Harris@hmc.edu 9 January 2021
// Modified: // Modified:
// //
// Purpose: Data cache unit // Purpose: Data memory
// Top level of the memory-stage hart logic // Top level of the memory-stage hart logic
// Contains data cache, subword read/write datapath, interface to external bus // Contains data cache, DTLB, subword read/write datapath, interface to external bus
// //
// A component of the Wally configurable RISC-V project. // A component of the Wally configurable RISC-V project.
// //
@ -27,7 +27,7 @@
`include "wally-config.vh" `include "wally-config.vh"
module dcu ( module dmem (
input logic [1:0] MemRWM, input logic [1:0] MemRWM,
output logic [1:0] MemRWdcuoutM, output logic [1:0] MemRWdcuoutM,
output logic DataMisalignedM, output logic DataMisalignedM,

2
wally-pipelined/src/wally/wallypipelinedhart.sv
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@ -93,7 +93,7 @@ module wallypipelinedhart (
ifu ifu(.*); // instruction fetch unit: PC, branch prediction, instruction cache ifu ifu(.*); // instruction fetch unit: PC, branch prediction, instruction cache
ieu ieu(.*); // inteber execution unit: integer register file, datapath and controller ieu ieu(.*); // inteber execution unit: integer register file, datapath and controller
dcu dcu(/*.Funct3M(InstrM[14:12]),*/ .*); // data cache unit dmem dmem(/*.Funct3M(InstrM[14:12]),*/ .*); // data cache unit
ahblite ebu( // *** make IRData InstrF ahblite ebu( // *** make IRData InstrF
.IPAdrF(PCF), .IReadF(1'b1), .IRData(), //.IReady(), .IPAdrF(PCF), .IReadF(1'b1), .IRData(), //.IReady(),