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https://github.com/openhwgroup/cvw
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Begin refactoring regression-wally
This commit is contained in:
Jordan Carlin
parent
32b62e9d0c
commit
1a2569e6f1
@ -4,6 +4,7 @@
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# regression-wally
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# David_Harris@Hmc.edu 25 January 2021
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# Modified by Jarred Allen <jaallen@g.hmc.edu> and many others
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# jcarlin@hmc.edu December 2024
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# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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#
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# Run a regression with multiple configurations in parallel and exit with
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@ -18,6 +19,14 @@ import multiprocessing
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from collections import namedtuple
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from multiprocessing import Pool, TimeoutError as MPTimeoutError
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# Globals
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WALLY = os.environ.get('WALLY')
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regressionDir = WALLY + '/sim'
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coveragesim = "questa" # Questa is required for code/functional coverage
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defaultsim = "verilator" # Default simulator for all other tests
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lockstepsim = "questa"
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##################################
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# Define lists of configurations and tests to run on each configuration
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##################################
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@ -38,6 +47,21 @@ tests = [
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["rv64i", ["arch64i"]]
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]
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tests64gc_fp = [
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["rv64gc", ["arch64f", "arch64d", "arch64zfh",
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"arch64f_fma", "arch64d_fma", "arch64zfh_fma",
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"arch64f_divsqrt", "arch64d_divsqrt", "arch64zfh_divsqrt",
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"arch64zfaf", "arch64zfad"]]
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]
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# Separate out floating-point tests for RV64 to speed up coverage
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tests64gc_nofp = [
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["rv64gc", ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m", "arch64zcb",
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"arch64zifencei", "arch64zicond", "arch64a_amo", "wally64a_lrsc", "wally64periph", "wally64priv",
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"arch64zbkb", "arch64zbkc", "arch64zbkx", "arch64zknd", "arch64zkne", "arch64zknh",
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"arch64zba", "arch64zbb", "arch64zbc", "arch64zbs"]] # add when working: "arch64zicboz"
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]
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# Separate test for short buildroot run through OpenSBI UART output
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tests_buildrootshort = [
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["buildroot", ["buildroot"], ["+INSTR_LIMIT=1400000"], # Instruction limit gets to first OpenSBI UART output
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@ -55,22 +79,6 @@ tests_buildrootbootlockstep = [
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"WallyHostname login: ", "buildroot_uart.out"]
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]
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# Separate out floating-point tests for RV64 to speed up coverage
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tests64gc_nofp = [
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["rv64gc", ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m", "arch64zcb",
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"arch64zifencei", "arch64zicond", "arch64a_amo", "wally64a_lrsc", "wally64periph", "wally64priv",
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"arch64zbkb", "arch64zbkc", "arch64zbkx", "arch64zknd", "arch64zkne", "arch64zknh",
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"arch64zba", "arch64zbb", "arch64zbc", "arch64zbs"]] # add when working: "arch64zicboz"
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]
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tests64gc_fp = [
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["rv64gc", ["arch64f", "arch64d", "arch64zfh",
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"arch64f_fma", "arch64d_fma", "arch64zfh_fma",
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"arch64f_divsqrt", "arch64d_divsqrt", "arch64zfh_divsqrt",
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"arch64zfaf", "arch64zfad"]]
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]
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derivconfigtests = [
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# memory system
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["tlb2_rv32gc", ["wally32priv"]],
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@ -182,7 +190,6 @@ derivconfigtests = [
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]
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bpredtests = [
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["nobpred_rv32gc", ["rv32i"]],
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["bpred_TWOBIT_6_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_TWOBIT_8_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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@ -231,11 +238,38 @@ bpredtests = [
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["bpred_GSHARE_10_10_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"]
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]
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testfloatdivconfigs = [
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"fdh_div_2_1_rv32gc", "fdh_div_2_1_rv64gc", "fdh_div_2_2_rv32gc",
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"fdh_div_2_2_rv64gc", "fdh_div_2_4_rv32gc", "fdh_div_2_4_rv64gc",
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"fdh_div_4_1_rv32gc", "fdh_div_4_1_rv64gc", "fdh_div_4_2_rv32gc",
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"fdh_div_4_2_rv64gc", "fdh_div_4_4_rv32gc", "fdh_div_4_4_rv64gc",
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"fd_div_2_1_rv32gc", "fd_div_2_1_rv64gc", "fd_div_2_2_rv32gc",
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"fd_div_2_2_rv64gc", "fd_div_2_4_rv32gc", "fd_div_2_4_rv64gc",
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"fd_div_4_1_rv32gc", "fd_div_4_1_rv64gc", "fd_div_4_2_rv32gc",
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"fd_div_4_2_rv64gc", "fd_div_4_4_rv32gc", "fd_div_4_4_rv64gc",
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"fdqh_div_2_1_rv32gc", "fdqh_div_2_1_rv64gc", "fdqh_div_2_2_rv32gc",
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"fdqh_div_2_2_rv64gc", "fdqh_div_2_4_rv32gc", "fdqh_div_2_4_rv64gc",
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"fdqh_div_4_1_rv32gc", "fdqh_div_4_1_rv64gc", "fdqh_div_4_2_rv32gc",
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"fdqh_div_4_2_rv64gc", "fdqh_div_4_4_rv32gc", "fdqh_div_4_4_rv64gc",
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"fdq_div_2_1_rv32gc", "fdq_div_2_1_rv64gc", "fdq_div_2_2_rv32gc",
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"fdq_div_2_2_rv64gc", "fdq_div_2_4_rv32gc", "fdq_div_2_4_rv64gc",
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"fdq_div_4_1_rv32gc", "fdq_div_4_1_rv64gc", "fdq_div_4_2_rv32gc",
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"fdq_div_4_2_rv64gc", "fdq_div_4_4_rv32gc", "fdq_div_4_4_rv64gc",
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"fh_div_2_1_rv32gc", "fh_div_2_1_rv64gc", "fh_div_2_2_rv32gc",
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"fh_div_2_2_rv64gc", "fh_div_2_4_rv32gc", "fh_div_2_4_rv64gc",
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"fh_div_4_1_rv32gc", "fh_div_4_1_rv64gc", "fh_div_4_2_rv32gc",
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"fh_div_4_2_rv64gc", "fh_div_4_4_rv32gc", "fh_div_4_4_rv64gc",
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"f_div_2_1_rv32gc", "f_div_2_1_rv64gc", "f_div_2_2_rv32gc",
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"f_div_2_2_rv64gc", "f_div_2_4_rv32gc", "f_div_2_4_rv64gc",
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"f_div_4_1_rv32gc", "f_div_4_1_rv64gc", "f_div_4_2_rv32gc",
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"f_div_4_2_rv64gc", "f_div_4_4_rv32gc", "f_div_4_4_rv64gc"
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]
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# list of tests not supported by ImperasDV yet that should be waived during lockstep testing
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lockstepwaivers = [
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"WALLY-q-01.S_ref.elf", # Q extension is not supported by ImperasDV
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"coverage_tlbMisaligned.elf", # Issue 976: ImperasDV bug disagrees with Wally related to misaligned pages when PBMT makes page uncachable
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"WALLY-cbom-01.S_ref.elf" #, # cbom extension is not supported by ImperasDV because there is no cache model in ImperasDV
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"WALLY-cbom-01.S_ref.elf", # cbom extension is not supported by ImperasDV because there is no cache model in ImperasDV
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]
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##################################
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@ -263,9 +297,9 @@ class bcolors:
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BOLD = '\033[1m'
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UNDERLINE = '\033[4m'
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def addTests(tests, sim):
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def addTests(testList, sim, coverStr, configs):
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sim_logdir = f"{WALLY}/sim/{sim}/logs/"
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for test in tests:
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for test in testList:
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config = test[0]
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suites = test[1]
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args = f" --args {test[2]}" if len(test) >= 3 else ""
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@ -283,34 +317,18 @@ def addTests(tests, sim):
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configs.append(tc)
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def addTestsByDir(testDir, config, sim, lockstepMode=0):
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if os.path.isdir(testDir):
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def addTestsByDir(testDir, config, sim, coverStr, configs, lockstepMode=0):
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if not os.path.isdir(testDir):
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print(f"Error: Directory not found: {testDir}")
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sys.exit(1)
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sim_logdir = f"{WALLY}/sim/{sim}/logs/"
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if coverStr == "--fcov": # use --fcov in place of --lockstep
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cmdPrefix=f"wsim --sim {sim} {coverStr} {config}"
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gs="Mismatches : 0"
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if ("cvw-arch-verif/tests" in testDir and "priv" not in testDir):
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fileEnd = "ALL.elf"
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else:
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fileEnd = ".elf"
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elif coverStr == "--ccov":
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cmdPrefix=f"wsim --sim {sim} {coverStr} {config}"
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gs="Single Elf file tests are not signatured verified."
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if ("cvw-arch-verif/tests" in testDir and "priv" not in testDir):
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fileEnd = "ALL.elf"
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else:
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fileEnd = ".elf"
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elif lockstepMode:
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cmdPrefix=f"wsim --lockstep --sim {sim} {config}"
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gs="Mismatches : 0"
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fileEnd = ".elf"
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else:
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cmdPrefix=f"wsim --sim {sim} {config}"
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gs="Single Elf file tests are not signatured verified."
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fileEnd = ".elf"
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cmdPrefix = f"wsim --sim {sim} {coverStr} {'--lockstep' if lockstepMode else ''} {config}"
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gs = "Mismatches : 0" if lockstepMode or coverStr == "--fcov" else "Single Elf file tests are not signatured verified."
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# fcov/ccov lockstep only runs on WALLY-COV-ALL.elf files; other lockstep runs on all files
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fileEnd = "ALL.elf" if "cvw-arch-verif/tests" in testDir and "priv" not in testDir and (coverStr == "--fcov" or coverStr == "--ccov") else ".elf"
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for dirpath, _, filenames in os.walk(os.path.abspath(testDir)):
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for file in filenames:
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# fcov lockstep only runs on WALLY-COV-ALL.elf files; other lockstep runs on all files
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if file.endswith(fileEnd):
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fullfile = os.path.join(dirpath, file)
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fields = fullfile.rsplit('/', 3)
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@ -329,9 +347,6 @@ def addTestsByDir(testDir, config, sim, lockstepMode=0):
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grepstr=gs,
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grepfile = sim_log)
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configs.append(tc)
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else:
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print(f"Error: Directory not found: {testDir}")
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sys.exit(1)
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def search_log_for_text(text, grepfile):
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"""Search through the given log file for text, returning True if it is found or False if it is not"""
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@ -365,20 +380,7 @@ def run_test_case(config, dryrun: bool = False):
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print(f" Check {grepfile}", flush=True)
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return 1
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##################################
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# Main body
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##################################
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WALLY = os.environ.get('WALLY')
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regressionDir = WALLY + '/sim'
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os.chdir(regressionDir)
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coveragesim = "questa" # Questa is required for code/functional coverage
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#defaultsim = "questa" # Default simulator for all other tests; change to Verilator when flow is ready
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defaultsim = "verilator" # Default simulator for all other tests
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lockstepsim = "questa"
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def parse_args():
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parser = argparse.ArgumentParser()
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parser.add_argument("--ccov", help="Code Coverage", action="store_true")
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parser.add_argument("--fcov", help="Functional Coverage", action="store_true")
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@ -387,8 +389,9 @@ parser.add_argument("--buildroot", help="Include Buildroot Linux boot test (take
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parser.add_argument("--testfloat", help="Include Testfloat floating-point unit tests", action="store_true")
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parser.add_argument("--fp", help="Include floating-point tests in coverage (slower runtime)", action="store_true") # Currently not used
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parser.add_argument("--dryrun", help="Print commands invoked to console without running regression", action="store_true")
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args = parser.parse_args()
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return parser.parse_args()
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def process_args(args):
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if args.nightly:
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nightMode = "--nightly"
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sims = ["questa", "verilator", "vcs"] # exercise all simulators; can omit a sim if no license is available
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@ -396,14 +399,16 @@ else:
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nightMode = ""
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sims = [defaultsim]
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if args.ccov: # only run RV64GC tests in coverage mode
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coverStr = '--ccov'
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elif args.fcov: # only run RV64GC tests in lockstep in coverage mode
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coverStr = '--fcov'
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if args.ccov:
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coverStr = "--ccov"
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elif args.fcov:
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coverStr = "--fcov"
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else:
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coverStr = ''
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coverStr = ""
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return nightMode, sims, coverStr
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def selectTests(nightMode, args, sims, coverStr):
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# Run Lint
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configs = [
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TestCase(
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@ -414,37 +419,34 @@ configs = [
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grepfile = f"{WALLY}/sim/verilator/logs/all_lints.log")
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]
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# run full buildroot boot simulation (slow) if buildroot flag is set. Start it early to overlap with other tests
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if args.buildroot:
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# addTests(tests_buildrootboot, defaultsim) # non-lockstep with Verilator runs in about 2 hours
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addTests(tests_buildrootbootlockstep, lockstepsim) # lockstep with Questa and ImperasDV runs overnight
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addTests(tests_buildrootbootlockstep, lockstepsim, coverStr, configs) # lockstep with Questa and ImperasDV runs overnight
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if args.ccov: # only run RV64GC tests on Questa in code coverage mode
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addTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv64/", "rv64gc", coveragesim)
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addTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/priv/rv64/", "rv64gc", coveragesim)
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addTestsByDir(WALLY+"/tests/coverage/", "rv64gc", coveragesim)
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addTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv64/", "rv64gc", coveragesim, coverStr, configs)
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addTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/priv/rv64/", "rv64gc", coveragesim, coverStr, configs)
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addTestsByDir(WALLY+"/tests/coverage/", "rv64gc", coveragesim, coverStr, configs)
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elif args.fcov: # run tests in lockstep in functional coverage mode
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addTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv32/", "rv32gc", coveragesim)
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addTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv64/", "rv64gc", coveragesim)
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addTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/priv/rv32/", "rv32gc", coveragesim)
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addTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/priv/rv64/", "rv64gc", coveragesim)
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addTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv32/", "rv32gc", coveragesim, coverStr, configs)
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addTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv64/", "rv64gc", coveragesim, coverStr, configs)
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addTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/priv/rv32/", "rv32gc", coveragesim, coverStr, configs)
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addTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/priv/rv64/", "rv64gc", coveragesim, coverStr, configs)
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else:
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for sim in sims:
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if not (args.buildroot and sim == lockstepsim): # skip short buildroot sim if running long one
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addTests(tests_buildrootshort, sim)
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addTests(tests, sim)
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addTests(tests64gc_nofp, sim)
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addTests(tests64gc_fp, sim)
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addTests(tests_buildrootshort, sim, coverStr, configs)
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addTests(tests, sim, coverStr, configs)
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addTests(tests64gc_nofp, sim, coverStr, configs)
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addTests(tests64gc_fp, sim, coverStr, configs)
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# run derivative configurations and lockstep tests in nightly regression
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if args.nightly:
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addTestsByDir(WALLY+"/tests/coverage", "rv64gc", lockstepsim, 1)
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addTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv64i_m", "rv64gc", lockstepsim, 1)
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addTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv32i_m", "rv32gc", lockstepsim, 1)
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addTests(derivconfigtests, defaultsim)
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addTestsByDir(WALLY+"/tests/coverage", "rv64gc", lockstepsim, 1, coverStr, configs)
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addTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv64i_m", "rv64gc", lockstepsim, coverStr, configs, 1)
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addTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv32i_m", "rv32gc", lockstepsim, coverStr, configs, 1)
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addTests(derivconfigtests, defaultsim, coverStr, configs)
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# addTests(bpredtests, defaultsim) # This is currently broken in regression due to something related to the new wsim script.
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# testfloat tests
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@ -466,34 +468,6 @@ if (args.testfloat or args.nightly): # for nightly, run testfloat along with oth
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grepstr="All Tests completed with 0 errors",
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grepfile = sim_log)
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configs.append(tc)
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testfloatdivconfigs = [
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"fdh_div_2_1_rv32gc", "fdh_div_2_1_rv64gc", "fdh_div_2_2_rv32gc",
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"fdh_div_2_2_rv64gc", "fdh_div_2_4_rv32gc", "fdh_div_2_4_rv64gc",
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"fdh_div_4_1_rv32gc", "fdh_div_4_1_rv64gc", "fdh_div_4_2_rv32gc",
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"fdh_div_4_2_rv64gc", "fdh_div_4_4_rv32gc", "fdh_div_4_4_rv64gc",
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"fd_div_2_1_rv32gc", "fd_div_2_1_rv64gc", "fd_div_2_2_rv32gc",
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"fd_div_2_2_rv64gc", "fd_div_2_4_rv32gc", "fd_div_2_4_rv64gc",
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"fd_div_4_1_rv32gc", "fd_div_4_1_rv64gc", "fd_div_4_2_rv32gc",
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"fd_div_4_2_rv64gc", "fd_div_4_4_rv32gc", "fd_div_4_4_rv64gc",
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"fdqh_div_2_1_rv32gc", "fdqh_div_2_1_rv64gc", "fdqh_div_2_2_rv32gc",
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"fdqh_div_2_2_rv64gc", "fdqh_div_2_4_rv32gc", "fdqh_div_2_4_rv64gc",
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"fdqh_div_4_1_rv32gc", "fdqh_div_4_1_rv64gc", "fdqh_div_4_2_rv32gc",
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"fdqh_div_4_2_rv64gc", "fdqh_div_4_4_rv32gc", "fdqh_div_4_4_rv64gc",
|
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"fdq_div_2_1_rv32gc", "fdq_div_2_1_rv64gc", "fdq_div_2_2_rv32gc",
|
||||
"fdq_div_2_2_rv64gc", "fdq_div_2_4_rv32gc", "fdq_div_2_4_rv64gc",
|
||||
"fdq_div_4_1_rv32gc", "fdq_div_4_1_rv64gc", "fdq_div_4_2_rv32gc",
|
||||
"fdq_div_4_2_rv64gc", "fdq_div_4_4_rv32gc", "fdq_div_4_4_rv64gc",
|
||||
"fh_div_2_1_rv32gc", "fh_div_2_1_rv64gc", "fh_div_2_2_rv32gc",
|
||||
"fh_div_2_2_rv64gc", "fh_div_2_4_rv32gc", "fh_div_2_4_rv64gc",
|
||||
"fh_div_4_1_rv32gc", "fh_div_4_1_rv64gc", "fh_div_4_2_rv32gc",
|
||||
"fh_div_4_2_rv64gc", "fh_div_4_4_rv32gc", "fh_div_4_4_rv64gc",
|
||||
"f_div_2_1_rv32gc", "f_div_2_1_rv64gc", "f_div_2_2_rv32gc",
|
||||
"f_div_2_2_rv64gc", "f_div_2_4_rv32gc", "f_div_2_4_rv64gc",
|
||||
"f_div_4_1_rv32gc", "f_div_4_1_rv64gc", "f_div_4_2_rv32gc",
|
||||
"f_div_4_2_rv64gc", "f_div_4_4_rv32gc", "f_div_4_4_rv64gc"
|
||||
]
|
||||
for config in testfloatdivconfigs:
|
||||
# div test case
|
||||
tests = ["div", "sqrt", "cvtint", "cvtfp"]
|
||||
@ -508,11 +482,14 @@ if (args.testfloat or args.nightly): # for nightly, run testfloat along with oth
|
||||
grepstr="All Tests completed with 0 errors",
|
||||
grepfile = f"{WALLY}/sim/{testfloatsim}/logs/{config}_{test}.log")
|
||||
configs.append(tc)
|
||||
return configs
|
||||
|
||||
|
||||
def main():
|
||||
def main(args):
|
||||
"""Run the tests and count the failures"""
|
||||
# global configs, args
|
||||
nightMode, sims, coverStr = process_args(args)
|
||||
configs = selectTests(nightMode, args, sims, coverStr)
|
||||
|
||||
os.chdir(regressionDir)
|
||||
dirs = ["questa/logs", "questa/wkdir", "verilator/logs", "verilator/wkdir", "vcs/logs", "vcs/wkdir"]
|
||||
for d in dirs:
|
||||
@ -561,4 +538,5 @@ def main():
|
||||
return num_fail
|
||||
|
||||
if __name__ == '__main__':
|
||||
sys.exit(main())
|
||||
args = parse_args()
|
||||
sys.exit(main(args))
|
||||
|
||||
Loading…
Reference in New Issue
Block a user