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busybear: slight testbench update

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Noah Boorstin 2021-03-05 19:00:40 +00:00
parent f48af209c4
commit 1a11b60664
1 changed files with 1 additions and 1 deletions
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wally-pipelined/testbench/testbench-busybear.sv
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@ -337,7 +337,7 @@ module testbench_busybear();
logic [31:0] InstrMask; logic [31:0] InstrMask;
logic forcedInstr; logic forcedInstr;
logic [63:0] lastPCF; logic [63:0] lastPCF;
always @(dut.PCF or dut.hart.ifu.InstrF) begin always @(dut.PCF or dut.hart.ifu.InstrF or reset) begin
if(~HWRITE) begin if(~HWRITE) begin
#3; #3;
if (~reset && dut.hart.ifu.InstrF[15:0] !== {16{1'bx}}) begin if (~reset && dut.hart.ifu.InstrF[15:0] !== {16{1'bx}}) begin