From 1a00e7bbeef2e89f8170f6f58163a30146990bf5 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 13 Nov 2022 21:36:12 -0600 Subject: [PATCH] Changed names of cache signals. --- pipelined/regression/fpga-wave.do | 2 +- pipelined/regression/wave.do | 2 +- pipelined/src/cache/cache.sv | 14 +++++++------- pipelined/src/cache/cacheway.sv | 4 ++-- pipelined/src/generic/mem/sram1p1rw.sv | 2 +- pipelined/src/ifu/ifu.sv | 2 +- pipelined/src/lsu/lsu.sv | 2 +- 7 files changed, 14 insertions(+), 14 deletions(-) diff --git a/pipelined/regression/fpga-wave.do b/pipelined/regression/fpga-wave.do index 41c3a2f01..f2f4ee116 100644 --- a/pipelined/regression/fpga-wave.do +++ b/pipelined/regression/fpga-wave.do @@ -318,7 +318,7 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/WriteDataM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FinalWriteData +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteData add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheFetchLine diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do index ed41ea6ed..99112e4c3 100644 --- a/pipelined/regression/wave.do +++ b/pipelined/regression/wave.do @@ -345,7 +345,7 @@ add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /t add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FinalWriteData +add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteData add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay add wave -noupdate -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit add wave -noupdate -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index 0761728b3..ec1ab7941 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -43,7 +43,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE input logic [11:0] NextAdr, // virtual address, but we only use the lower 12 bits. input logic [`PA_BITS-1:0] PAdr, // physical address input logic [(WORDLEN-1)/8:0] ByteMask, - input logic [WORDLEN-1:0] FinalWriteData, + input logic [WORDLEN-1:0] CacheWriteData, output logic CacheCommitted, output logic CacheStall, // to performance counters to cpu @@ -71,7 +71,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE logic SelAdr; logic [SETLEN-1:0] RAdr; - logic [LINELEN-1:0] CacheWriteData; + logic [LINELEN-1:0] LineWriteData; logic ClearValid; logic ClearDirty; logic [LINELEN-1:0] ReadDataLineWay [NUMWAYS-1:0]; @@ -124,7 +124,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE // Array of cache ways, along with victim, hit, dirty, and read merging logic cacheway #(NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN) - CacheWays[NUMWAYS-1:0](.clk, .reset, .ce(SRAMEnable), .RAdr, .PAdr, .CacheWriteData, .LineByteMask, + CacheWays[NUMWAYS-1:0](.clk, .reset, .ce(SRAMEnable), .RAdr, .PAdr, .LineWriteData, .LineByteMask, .SetValidWay, .ClearValidWay, .SetDirtyWay, .ClearDirtyWay, .SelEvict, .VictimWay, .FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .VictimDirtyWay, .VictimTagWay, .Flush, .Invalidate(InvalidateCache)); @@ -156,8 +156,8 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE ///////////////////////////////////////////////////////////////////////////////////////////// // Write Path: Write data and address. Muxes between writes from bus and writes from CPU. ///////////////////////////////////////////////////////////////////////////////////////////// - logic [LINELEN-1:0] FinalWriteDataDup; - assign FinalWriteDataDup = {WORDSPERLINE{FinalWriteData}}; + logic [LINELEN-1:0] CacheWriteDataDup; + assign CacheWriteDataDup = {WORDSPERLINE{CacheWriteData}}; onehotdecoder #(LOGCWPL) adrdec( .bin(PAdr[LOGCWPL+LOGLLENBYTES-1:LOGLLENBYTES]), .decoded(MemPAdrDecoded)); @@ -169,8 +169,8 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE assign LineByteMask = ~SetValid & ~SetDirty ? '0 : ~SetValid & SetDirty ? DemuxedByteMask : '1; // if store hit only enable the word and subword bytes, else write all bytes. for(index = 0; index < LINELEN/8; index++) begin - mux2 #(8) WriteDataMux(.d0(FinalWriteDataDup[8*index+7:8*index]), - .d1(FetchBuffer[8*index+7:8*index]), .s(LineByteMux[index]), .y(CacheWriteData[8*index+7:8*index])); + mux2 #(8) WriteDataMux(.d0(CacheWriteDataDup[8*index+7:8*index]), + .d1(FetchBuffer[8*index+7:8*index]), .s(LineByteMux[index]), .y(LineWriteData[8*index+7:8*index])); end mux3 #(`PA_BITS) CacheBusAdrMux(.d0({PAdr[`PA_BITS-1:OFFSETLEN], {OFFSETLEN{1'b0}}}), diff --git a/pipelined/src/cache/cacheway.sv b/pipelined/src/cache/cacheway.sv index 4776aeaf1..7401a53ac 100644 --- a/pipelined/src/cache/cacheway.sv +++ b/pipelined/src/cache/cacheway.sv @@ -38,7 +38,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, input logic [$clog2(NUMLINES)-1:0] RAdr, input logic [`PA_BITS-1:0] PAdr, - input logic [LINELEN-1:0] CacheWriteData, + input logic [LINELEN-1:0] LineWriteData, input logic SetValidWay, input logic ClearValidWay, input logic SetDirtyWay, @@ -109,7 +109,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, for(words = 0; words < NUMSRAM; words++) begin: word sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(SRAMLEN)) CacheDataMem(.clk, .ce, .addr(RAdr), .dout(ReadDataLine[SRAMLEN*(words+1)-1:SRAMLEN*words]), - .din(CacheWriteData[SRAMLEN*(words+1)-1:SRAMLEN*words]), + .din(LineWriteData[SRAMLEN*(words+1)-1:SRAMLEN*words]), .we(SelectedWriteWordEn & ~Flush), .bwe(FinalByteMask[SRAMLENINBYTES*(words+1)-1:SRAMLENINBYTES*words])); end diff --git a/pipelined/src/generic/mem/sram1p1rw.sv b/pipelined/src/generic/mem/sram1p1rw.sv index b4aec9220..7dd3ec0ef 100644 --- a/pipelined/src/generic/mem/sram1p1rw.sv +++ b/pipelined/src/generic/mem/sram1p1rw.sv @@ -3,7 +3,7 @@ // // Written: ross1728@gmail.com May 3, 2021 // Basic sram with 1 read write port. -// When clk rises Addr and CacheWriteData are sampled. +// When clk rises Addr and LineWriteData are sampled. // Following the clk edge read data is output from the sampled Addr. // Write // diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 0798d25f5..65526977a 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -229,7 +229,7 @@ module ifu ( .SelHPTW('0), .CacheMiss(ICacheMiss), .CacheAccess(ICacheAccess), .ByteMask('0), .BeatCount('0), .SelBusBeat('0), - .FinalWriteData('0), + .CacheWriteData('0), .CacheRW(CacheRWF), .CacheAtomic('0), .FlushCache('0), .NextAdr(PCNextFSpill[11:0]), diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 1894eec61..cd4846e51 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -251,7 +251,7 @@ module lsu ( .clk, .reset, .CPUBusy, .SelBusBeat, .Flush(FlushW), .CacheRW(CacheRWM), .CacheAtomic(CacheAtomicM), .FlushCache(CacheFlushM), .NextAdr(IEUAdrE[11:0]), .PAdr(PAdrM), .ByteMask(ByteMaskM), .BeatCount(BeatCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]), - .FinalWriteData(LSUWriteDataM), .SelHPTW, + .CacheWriteData(LSUWriteDataM), .SelHPTW, .CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess), .CacheCommitted(DCacheCommittedM), .CacheBusAdr(DCacheBusAdr), .ReadDataWord(DCacheReadDataWordM),