diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv index a002bc2e5..b6b4af5c0 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv @@ -47,7 +47,7 @@ module fdivsqrt( output logic FDivBusyE, IFDivStartE, FDivDoneE, output logic [`NE+1:0] QeM, output logic [`DIVb:0] QmM, - output logic [`XLEN-1:0] FPIntDivResultM + output logic [`XLEN-1:0] FIntDivResultM ); // Floating-point division and square root module, with optional integer division and remainder @@ -97,5 +97,5 @@ module fdivsqrt( .QmM, .WZeroE, .DivStickyM, // Int-specific .nM, .mM, .ALTBM, .AsM, .BZeroM, .NegQuotM, .W64M, .RemOpM(Funct3M[1]), .AM, - .FPIntDivResultM); + .FIntDivResultM); endmodule \ No newline at end of file diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv index 86bd1efa1..84b3bfbac 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv @@ -41,7 +41,7 @@ module fdivsqrtpostproc( output logic [`DIVb:0] QmM, output logic WZeroE, output logic DivStickyM, - output logic [`XLEN-1:0] FPIntDivResultM + output logic [`XLEN-1:0] FIntDivResultM ); logic [`DIVb+3:0] W, Sum, DM; @@ -129,8 +129,8 @@ module fdivsqrtpostproc( if (`XLEN==64) begin mux2 #(64) resmux(IntDivResultM[`XLEN-1:0], {{(`XLEN-32){IntDivResultM[31]}}, IntDivResultM[31:0]}, // Sign extending in case of W64 - W64M, FPIntDivResultM); + W64M, FIntDivResultM); end else - assign FPIntDivResultM = IntDivResultM[`XLEN-1:0]; + assign FIntDivResultM = IntDivResultM[`XLEN-1:0]; end endmodule \ No newline at end of file diff --git a/pipelined/src/fpu/fhazard.sv b/pipelined/src/fpu/fhazard.sv index 653f3676a..db1f55223 100644 --- a/pipelined/src/fpu/fhazard.sv +++ b/pipelined/src/fpu/fhazard.sv @@ -54,7 +54,7 @@ module fhazard( // if the result will be FResM (can be taken from the memory stage) if(FResSelM == 2'b00) ForwardXE = 2'b10; // choose FResM // if the needed value is in the writeback stage - end else if ((Adr1E == RdW) & FRegWriteW) ForwardXE = 2'b01; // choose FPUResult64W + end else if ((Adr1E == RdW) & FRegWriteW) ForwardXE = 2'b01; // choose FResult64W // if the needed value is in the memory stage - input 2 @@ -62,7 +62,7 @@ module fhazard( // if the result will be FResM (can be taken from the memory stage) if(FResSelM == 2'b00) ForwardYE = 2'b10; // choose FResM // if the needed value is in the writeback stage - end else if ((Adr2E == RdW) & FRegWriteW) ForwardYE = 2'b01; // choose FPUResult64W + end else if ((Adr2E == RdW) & FRegWriteW) ForwardYE = 2'b01; // choose FResult64W // if the needed value is in the memory stage - input 3 @@ -70,7 +70,7 @@ module fhazard( // if the result will be FResM (can be taken from the memory stage) if(FResSelM == 2'b00) ForwardZE = 2'b10; // choose FResM // if the needed value is in the writeback stage - end else if ((Adr3E == RdW) & FRegWriteW) ForwardZE = 2'b01; // choose FPUResult64W + end else if ((Adr3E == RdW) & FRegWriteW) ForwardZE = 2'b01; // choose FResult64W end diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv index 221cf7e08..170e46886 100755 --- a/pipelined/src/fpu/fpu.sv +++ b/pipelined/src/fpu/fpu.sv @@ -60,7 +60,7 @@ module fpu ( input logic [`FLEN-1:0] ReadDataW, // Read data (from LSU) output logic [`XLEN-1:0] FCvtIntResW, // convert result to to be written to integer register (to IEU) output logic FCvtIntW, // select FCvtIntRes (to IEU) - output logic [`XLEN-1:0] FPIntDivResultW // Result from integer division (to IEU) + output logic [`XLEN-1:0] FIntDivResultW // Result from integer division (to IEU) ); // RISC-V FPU specifics: @@ -133,7 +133,7 @@ module fpu ( logic [`NE+1:0] QeM; // fdivsqrt exponent logic DivStickyM; // fdivsqrt sticky bit logic FDivDoneE, IFDivStartE; // fdivsqrt control signals - logic [`XLEN-1:0] FPIntDivResultM; // fdivsqrt integer division result (for IEU) + logic [`XLEN-1:0] FIntDivResultM; // fdivsqrt integer division result (for IEU) // result and flag signals logic [`XLEN-1:0] ClassResE; // classify result @@ -147,7 +147,7 @@ module fpu ( logic [`FLEN-1:0] SgnResE; // sign injection result logic [`FLEN-1:0] PreFpResE, PreFpResM; // selected result that is ready in the memory stage logic PreNVE, PreNVM; // selected flag that is ready in the memory stage - logic [`FLEN-1:0] FPUResultW; // final FP result being written to the FP register + logic [`FLEN-1:0] FResultW; // final FP result being written to the FP register // other signals logic [`FLEN-1:0] AlignedSrcAE; // align SrcA to the floating point format logic [`FLEN-1:0] BoxedZeroE; // Zero value for Z for multiplication, with NaN boxing if needed @@ -177,7 +177,7 @@ module fpu ( // FP register file fregfile fregfile (.clk, .reset, .we4(FRegWriteW), .a1(InstrD[19:15]), .a2(InstrD[24:20]), .a3(InstrD[31:27]), - .a4(RdW), .wd4(FPUResultW), + .a4(RdW), .wd4(FResultW), .rd1(FRD1D), .rd2(FRD2D), .rd3(FRD3D)); // D/E pipeline registers @@ -203,9 +203,9 @@ module fpu ( .XEnD, .YEnD, .ZEnD, .FPUStallD, .ForwardXE, .ForwardYE, .ForwardZE); // forwarding muxs - mux3 #(`FLEN) fxemux (FRD1E, FPUResultW, PreFpResM, ForwardXE, XE); - mux3 #(`FLEN) fyemux (FRD2E, FPUResultW, PreFpResM, ForwardYE, PreYE); - mux3 #(`FLEN) fzemux (FRD3E, FPUResultW, PreFpResM, ForwardZE, PreZE); + mux3 #(`FLEN) fxemux (FRD1E, FResultW, PreFpResM, ForwardXE, XE); + mux3 #(`FLEN) fyemux (FRD2E, FResultW, PreFpResM, ForwardYE, PreYE); + mux3 #(`FLEN) fzemux (FRD3E, FResultW, PreFpResM, ForwardZE, PreZE); generate @@ -268,7 +268,7 @@ module fpu ( .XInfE, .YInfE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, .FDivStartE, .IDivStartE, .XsE, .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .IntDivE, .W64E, .StallM, .FlushE, .DivStickyM, .FDivBusyE, .IFDivStartE, .FDivDoneE, .QeM, - .QmM, .FPIntDivResultM /*, .DivDone(DivDoneM) */); + .QmM, .FIntDivResultM /*, .DivDone(DivDoneM) */); // // compare @@ -388,7 +388,7 @@ module fpu ( // M/W pipe registers flopenrc #(`FLEN) MWRegFp(clk, reset, FlushW, ~StallW, FpResM, FpResW); flopenrc #(`XLEN) MWRegIntCvtRes(clk, reset, FlushW, ~StallW, FCvtIntResM, FCvtIntResW); - flopenrc #(`XLEN) MWRegIntDivRes(clk, reset, FlushW, ~StallW, FPIntDivResultM, FPIntDivResultW); + flopenrc #(`XLEN) MWRegIntDivRes(clk, reset, FlushW, ~StallW, FIntDivResultM, FIntDivResultW); // BEGIN WRITEBACK STAGE @@ -403,6 +403,6 @@ module fpu ( ////////////////////////////////////////////////////////////////////////////////////////// // select the result to be written to the FP register - mux2 #(`FLEN) FPUResultMux (FpResW, ReadDataW, FResSelW[1], FPUResultW); + mux2 #(`FLEN) FResultMux (FpResW, ReadDataW, FResSelW[1], FResultW); endmodule // fpu diff --git a/pipelined/src/ieu/datapath.sv b/pipelined/src/ieu/datapath.sv index 26eda940c..346fab14b 100644 --- a/pipelined/src/ieu/datapath.sv +++ b/pipelined/src/ieu/datapath.sv @@ -59,7 +59,7 @@ module datapath ( input logic [`XLEN-1:0] FCvtIntResW, input logic [`XLEN-1:0] ReadDataW, input logic [`XLEN-1:0] CSRReadValW, MDUResultW, - input logic [`XLEN-1:0] FPIntDivResultW, + input logic [`XLEN-1:0] FIntDivResultW, // Hazard Unit signals output logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E, output logic [4:0] RdE, RdM, RdW @@ -122,7 +122,7 @@ module datapath ( mux2 #(`XLEN) resultmuxM(IEUResultM, FIntResM, FWriteIntM, IFResultM); mux2 #(`XLEN) cvtresultmuxW(IFResultW, FCvtIntResW, FCvtIntW, IFCvtResultW); if (`IDIV_ON_FPU) begin - mux2 #(`XLEN) divresultmuxW(MDUResultW, FPIntDivResultW, IntDivW, MulDivResultW); + mux2 #(`XLEN) divresultmuxW(MDUResultW, FIntDivResultW, IntDivW, MulDivResultW); end else begin assign MulDivResultW = MDUResultW; end diff --git a/pipelined/src/ieu/ieu.sv b/pipelined/src/ieu/ieu.sv index 23df64e69..20fbe3a9d 100644 --- a/pipelined/src/ieu/ieu.sv +++ b/pipelined/src/ieu/ieu.sv @@ -54,7 +54,7 @@ module ieu ( output logic InvalidateICacheM, FlushDCacheM, // Writeback stage - input logic [`XLEN-1:0] FPIntDivResultW, + input logic [`XLEN-1:0] FIntDivResultW, input logic [`XLEN-1:0] CSRReadValW, MDUResultW, input logic [`XLEN-1:0] FCvtIntResW, output logic [4:0] RdW, @@ -104,7 +104,7 @@ module ieu ( .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, .StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataM, .FCvtIntW, .StallW, .FlushW, .RegWriteW, .IntDivW, .SquashSCW, .ResultSrcW, .ReadDataW, .FCvtIntResW, - .CSRReadValW, .MDUResultW, .FPIntDivResultW, .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW); + .CSRReadValW, .MDUResultW, .FIntDivResultW, .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW); forward fw( .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW, diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index 828091111..b48dcd28c 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -93,7 +93,7 @@ module wallypipelinedcore ( logic FCvtIntStallD; logic FpLoadStoreM; logic [4:0] SetFflagsM; - logic [`XLEN-1:0] FPIntDivResultW; + logic [`XLEN-1:0] FIntDivResultW; // memory management unit signals logic ITLBWriteF; @@ -223,7 +223,7 @@ module wallypipelinedcore ( .RdE, .RdM, .FIntResM, .InvalidateICacheM, .FlushDCacheM, // Writeback stage - .CSRReadValW, .MDUResultW, .FPIntDivResultW, + .CSRReadValW, .MDUResultW, .FIntDivResultW, .RdW, .ReadDataW(ReadDataW[`XLEN-1:0]), .InstrValidM, .FCvtIntResW, @@ -401,7 +401,7 @@ module wallypipelinedcore ( .FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage) .IllegalFPUInstrM, // Is the instruction an illegal fpu instruction .SetFflagsM, // FPU flags (to privileged unit) - .FPIntDivResultW + .FIntDivResultW ); // floating point unit end else begin // no F_SUPPORTED or D_SUPPORTED; tie outputs low assign FPUStallD = 0;