From 19ec874641623f28108aa8088f0033dbffcceafe Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 23 Feb 2022 10:16:12 -0600 Subject: [PATCH] Fixed bug with spill support and Instruction DA Page Faults. --- pipelined/src/ifu/ifu.sv | 6 ++-- pipelined/src/ifu/spillsupport.sv | 50 +++++++++++++++---------------- 2 files changed, 27 insertions(+), 29 deletions(-) diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 663639f8d..62518b263 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -125,8 +125,8 @@ module ifu ( if(`C_SUPPORTED) begin : SpillSupport spillsupport spillsupport(.clk, .reset, .StallF, .PCF, .PCPlusUpperF, .PCNextF, .InstrRawF, - .IFUCacheBusStallF, .ITLBMissF, .PCNextFSpill, .PCFSpill, - .SelNextSpillF, .PostSpillInstrRawF, .CompressedF); + .InstrDAPageFaultF, .IFUCacheBusStallF, .ITLBMissF, .PCNextFSpill, .PCFSpill, + .SelNextSpillF, .PostSpillInstrRawF, .CompressedF); end else begin : NoSpillSupport assign PCNextFSpill = PCNextF; assign PCFSpill = PCF; @@ -160,7 +160,7 @@ module ifu ( .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW); end else begin - assign {ITLBMissF, InstrAccessFaultF, InstrPageFaultF} = '0; + assign {ITLBMissF, InstrAccessFaultF, InstrPageFaultF, InstrDAPageFaultF} = '0; assign PCPF = PCFExt[`PA_BITS-1:0]; assign CacheableF = '1; end diff --git a/pipelined/src/ifu/spillsupport.sv b/pipelined/src/ifu/spillsupport.sv index a55155513..c84d7e82a 100644 --- a/pipelined/src/ifu/spillsupport.sv +++ b/pipelined/src/ifu/spillsupport.sv @@ -42,6 +42,7 @@ module spillsupport ( input logic [31:0] InstrRawF, input logic IFUCacheBusStallF, input logic ITLBMissF, + input logic InstrDAPageFaultF, output logic [`XLEN-1:0] PCNextFSpill, output logic [`XLEN-1:0] PCFSpill, output logic SelNextSpillF, @@ -50,44 +51,41 @@ module spillsupport ( localparam integer SPILLTHRESHOLD = (`IMEM == `MEM_CACHE) ? `ICACHE_LINELENINBITS/32 : 1; - logic [`XLEN-1:0] PCPlus2F; - logic TakeSpillF; - logic SpillF; - logic SelSpillF, SpillSaveF; - logic [15:0] SpillDataLine0; + logic [`XLEN-1:0] PCPlus2F; + logic TakeSpillF; + logic SpillF; + logic SelSpillF, SpillSaveF; + logic [15:0] SpillDataLine0; + typedef enum logic [1:0] {STATE_READY, STATE_SPILL} statetype; + (* mark_debug = "true" *) statetype CurrState, NextState; - // *** PLACE ALL THIS IN A MODULE - // this exists only if there are compressed instructions. - // reuse PC+2/4 circuitry to avoid needing a second CPA to add 2 - mux2 #(`XLEN) pcplus2mux(.d0({PCF[`XLEN-1:2], 2'b10}), .d1({PCPlusUpperF, 2'b00}), .s(PCF[1]), .y(PCPlus2F)); - mux2 #(`XLEN) pcnextspillmux(.d0(PCNextF), .d1(PCPlus2F), .s(SelNextSpillF), .y(PCNextFSpill)); + mux2 #(`XLEN) pcplus2mux(.d0({PCF[`XLEN-1:2], 2'b10}), .d1({PCPlusUpperF, 2'b00}), + .s(PCF[1]), .y(PCPlus2F)); + mux2 #(`XLEN) pcnextspillmux(.d0(PCNextF), .d1(PCPlus2F), .s(SelNextSpillF), + .y(PCNextFSpill)); mux2 #(`XLEN) pcspillmux(.d0(PCF), .d1(PCPlus2F), .s(SelSpillF), .y(PCFSpill)); assign SpillF = &PCF[$clog2(SPILLTHRESHOLD)+1:1]; - - typedef enum logic [1:0] {STATE_SPILL_READY, STATE_SPILL_SPILL} statetype; - (* mark_debug = "true" *) statetype CurrState, NextState; - + assign TakeSpillF = SpillF & ~IFUCacheBusStallF & ~(ITLBMissF | InstrDAPageFaultF); + always_ff @(posedge clk) - if (reset) CurrState <= #1 STATE_SPILL_READY; + if (reset) CurrState <= #1 STATE_READY; else CurrState <= #1 NextState; - assign TakeSpillF = SpillF & ~IFUCacheBusStallF & ~ITLBMissF; - always_comb begin case (CurrState) - STATE_SPILL_READY: if (TakeSpillF) NextState = STATE_SPILL_SPILL; - else NextState = STATE_SPILL_READY; - STATE_SPILL_SPILL: if(IFUCacheBusStallF | StallF) NextState = STATE_SPILL_SPILL; - else NextState = STATE_SPILL_READY; - default: NextState = STATE_SPILL_READY; + STATE_READY: if (TakeSpillF) NextState = STATE_SPILL; + else NextState = STATE_READY; + STATE_SPILL: if(IFUCacheBusStallF | StallF) NextState = STATE_SPILL; + else NextState = STATE_READY; + default: NextState = STATE_READY; endcase end - assign SelSpillF = (CurrState == STATE_SPILL_SPILL); - assign SelNextSpillF = (CurrState == STATE_SPILL_READY & TakeSpillF) | - (CurrState == STATE_SPILL_SPILL & IFUCacheBusStallF); - assign SpillSaveF = (CurrState == STATE_SPILL_READY) & TakeSpillF; + assign SelSpillF = (CurrState == STATE_SPILL); + assign SelNextSpillF = (CurrState == STATE_READY & TakeSpillF) | + (CurrState == STATE_SPILL & IFUCacheBusStallF); + assign SpillSaveF = (CurrState == STATE_READY) & TakeSpillF; flopenr #(16) SpillInstrReg(.clk(clk), .en(SpillSaveF),