Cleanup dtim and irom.

pipelined/src/ifu/ifu.sv

@@ -189,9 +189,11 @@ module ifu (
   assign IgnoreRequest = ITLBMissF | FlushD;
 
   // The IROM uses untranslated addresses, so it is not compatible with virtual memory.
-  if (`IROM_SUPPORTED) begin : irom 
+  if (`IROM_SUPPORTED) begin : irom
+	logic IROMce;
+	assign IROMce = ~GatedStallD | reset;
     assign IFURWF = 2'b10;
-    irom irom(.clk, .ce(~GatedStallD | reset), .Adr(PCNextFSpill[`XLEN-1:0]), .ReadData(IROMInstrF));
+    irom irom(.clk, .ce(IROMce), .Adr(PCNextFSpill[`XLEN-1:0]), .IROMInstrF);
   end else begin
     assign IFURWF = 2'b10;
   end

pipelined/src/ifu/irom.sv

@@ -26,23 +26,24 @@
 `include "wally-config.vh"
 
 module irom(
-  input logic               clk, ce,
+  input logic 			  clk, 
-  input logic [`XLEN-1:0]   Adr,
+  input logic 			  ce,        // Chip Enable.  0: Holds IROMInstrF constant
-  output logic [31:0]  ReadData
+  input logic [`XLEN-1:0] Adr,       // PCNextFSpill
+  output logic [31:0] 	  IROMInstrF // Instruction read data
 );
 
   localparam ADDR_WDITH = $clog2(`IROM_RANGE/8); 
   localparam OFFSET = $clog2(`XLEN/8);
 
-  logic [`XLEN-1:0] ReadDataFull;
+  logic [`XLEN-1:0] IROMInstrFFull;
 
-  rom1p1r #(ADDR_WDITH, `XLEN) rom(.clk, .ce, .addr(Adr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataFull));
+  rom1p1r #(ADDR_WDITH, `XLEN) rom(.clk, .ce, .addr(Adr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(IROMInstrFFull));
-  if (`XLEN == 32) assign ReadData = ReadDataFull;
+  if (`XLEN == 32) assign IROMInstrF = IROMInstrFFull;
   // have to delay Ardr[OFFSET-1] by 1 cycle
   else             begin
     logic AdrD;
     flopen #(1) AdrReg(clk, ce, Adr[OFFSET-1], AdrD);
-    assign ReadData = AdrD ? ReadDataFull[63:32] : ReadDataFull[31:0];
+    assign IROMInstrF = AdrD ? IROMInstrFFull[63:32] : IROMInstrFFull[31:0];
   end
 endmodule  
   

pipelined/src/lsu/dtim.sv

@@ -34,7 +34,7 @@ module dtim(
   input logic 				 FlushW,        
   input logic 				 ce,            // Chip Enable.  0: Holds ReadDataWordM
   input logic [1:0] 		 MemRWM,        // Read/Write control
-  input logic [`PA_BITS-1:0] AdrM,          // Execution stage memory address
+  input logic [`PA_BITS-1:0] DTIMAdr,       // No stall: Execution stage memory address. Stall: Memory stage memory address
   input logic [`LLEN-1:0] 	 WriteDataM,    // Write data from IEU
   input logic [`LLEN/8-1:0]  ByteMaskM,     // Selects which bytes within a word to write
   output logic [`LLEN-1:0] 	 ReadDataWordM  // Read data before subword selection
@@ -48,6 +48,6 @@ module dtim(
   assign we = MemRWM[0]  & ~FlushW;  // have to ignore write if Trap.
 
   ram1p1rwbe #(.DEPTH(`DTIM_RANGE/8), .WIDTH(`LLEN)) 
-    ram(.clk, .ce, .we, .bwe(ByteMaskM), .addr(AdrM[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataWordM), .din(WriteDataM));
+    ram(.clk, .ce, .we, .bwe(ByteMaskM), .addr(DTIMAdr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataWordM), .din(WriteDataM));
 endmodule  
   

pipelined/src/lsu/lsu.sv

@@ -232,7 +232,7 @@ module lsu (
     // **** fix ReadDataWordM to be LLEN. ByteMask is wrong length.
     // **** create config to support DTIM with floating point.
     dtim dtim(.clk, .ce(~GatedStallW), .MemRWM(DTIMMemRWM),
-              .AdrM(DTIMAdr), .FlushW, .WriteDataM(LSUWriteDataM), 
+              .DTIMAdr, .FlushW, .WriteDataM(LSUWriteDataM), 
               .ReadDataWordM(DTIMReadDataWordM[`XLEN-1:0]), .ByteMaskM(ByteMaskM[`XLEN/8-1:0]));
   end else begin
   end