diff --git a/pipelined/config/shared/wally-shared.vh b/pipelined/config/shared/wally-shared.vh
index 4ff665782..87d671032 100644
--- a/pipelined/config/shared/wally-shared.vh
+++ b/pipelined/config/shared/wally-shared.vh
@@ -101,8 +101,8 @@
 `define CORRSHIFTSZ ((`DIVRESLEN+`NF) > (3*`NF+8) ? (`DIVRESLEN+`NF) : (3*`NF+6))
 
 // division constants
-`define RADIX 32'h4
-`define DIVCOPIES 32'h1
+`define RADIX 32'h2
+`define DIVCOPIES 32'h4
 `define DIVLEN ((`NF < `XLEN) ? (`XLEN) : (`NF + 3))
 // `define DIVN (`NF < `XLEN ? `XLEN : `NF+1) // length of input
 `define DIVN (`NF < `XLEN ? `XLEN : `NF+3) // length of input
diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do
index f65a6dc8a..c86ee5707 100644
--- a/pipelined/regression/wave.do
+++ b/pipelined/regression/wave.do
@@ -559,6 +559,7 @@ add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/cachedp/AHBB
 add wave -noupdate /testbench/dut/core/ifu/bus/icache/cachedp/AHBBuscachefsm/WordCountFlag
 add wave -noupdate /testbench/dut/core/lsu/ByteMaskM
 add wave -noupdate /testbench/dut/core/fpu/fpu/FWriteDataM
+#add wave -group {Sqrt} -noupdate -recursive /testbench/dut/core/fpu/fpu/fdivsqrt/*
 TreeUpdate [SetDefaultTree]
 WaveRestoreCursors {{Cursor 2} {377526 ns} 0} {{Cursor 3} {377441 ns} 1} {{Cursor 4} {378225 ns} 1}
 quietly wave cursor active 1
diff --git a/pipelined/src/fpu/fdivsqrt.sv b/pipelined/src/fpu/fdivsqrt.sv
index 794dd7526..9f95fe7cf 100644
--- a/pipelined/src/fpu/fdivsqrt.sv
+++ b/pipelined/src/fpu/fdivsqrt.sv
@@ -73,4 +73,5 @@ module fdivsqrt(
                .StickyWSA, .XInfE, .YInfE, .NegSticky(NegSticky), .EarlyTermShiftE(EarlyTermShiftM));
   fdivsqrtiter fdivsqrtiter(.clk, .qn, .D, .LastSM, .LastC, .FirstSM, .FirstC, .SqrtE, .SqrtM, .X,.Dpreproc, .NegSticky, .FirstWS(WS), .FirstWC(WC), .NextWSN, .NextWCN, .DivStart(DivStartE), .Xe(XeE), .Ye(YeE), .XZeroE, .YZeroE,
                 .StickyWSA, .DivBusy, .Qm(QmM));
+//  fdivsqrtpostproc fdivsqrtpostproc();
 endmodule
\ No newline at end of file
diff --git a/pipelined/src/fpu/fdivsqrtfsm.sv b/pipelined/src/fpu/fdivsqrtfsm.sv
index 27d46cffd..227204cb5 100644
--- a/pipelined/src/fpu/fdivsqrtfsm.sv
+++ b/pipelined/src/fpu/fdivsqrtfsm.sv
@@ -69,7 +69,7 @@ module fdivsqrtfsm(
   logic WZeroDelayed, WZeroD; // *** later remove
 
   //flopen #($clog2(`DIVLEN/2+3)) durflop(clk, DivStart, CalcDur, Dur);
-  assign DivBusy = (state == BUSY);
+  assign DivBusy = (state == BUSY & ~DivDone);
   // calculate sticky bit
   //    - there is a chance that a value is subtracted infinitly, resulting in an exact QM result
   //      this is only a problem on radix 2 (and possibly maximally redundant 4) since minimally redundant
@@ -100,11 +100,11 @@ module fdivsqrtfsm(
     assign WZeroD = ((WS^WC)=={WS[`DIVb+2:0]|WC[`DIVb+2:0], 1'b0})|(((WS+WC+FZeroD)==0)&qn[`DIVCOPIES-1]);
   end else begin
     assign WZeroD = ((WS^WC)=={WS[`DIVb+2:0]|WC[`DIVb+2:0], 1'b0});
-  end
+  end 
 
   flopr #(1) WZeroReg(clk, reset | DivStart, WZero, WZeroDelayed);
-//  assign DivDone = (state == DONE) | (WZeroD & (state == BUSY));
-  assign DivDone = (state == DONE) | (WZeroDelayed & (state == BUSY));
+  assign DivDone = (state == DONE) | (WZeroD & (state == BUSY));
+//  assign DivDone = (state == DONE) | (WZeroDelayed & (state == BUSY));
   assign W = WC+WS;
   assign NegSticky = W[`DIVb+3];
   assign EarlyTermShiftE = step;
diff --git a/pipelined/src/fpu/fdivsqrtpostproc.sv b/pipelined/src/fpu/fdivsqrtpostproc.sv
new file mode 100644
index 000000000..ca88afb3c
--- /dev/null
+++ b/pipelined/src/fpu/fdivsqrtpostproc.sv
@@ -0,0 +1,62 @@
+///////////////////////////////////////////
+// fdivsqrtpostproc.sv
+//
+// Written: David_Harris@hmc.edu, me@KatherineParry.com, Cedar Turek
+// Modified:13 January 2022
+//
+// Purpose: Combined Divide and Square Root Floating Point and Integer Unit
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// MIT LICENSE
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
+// software and associated documentation files (the "Software"), to deal in the Software 
+// without restriction, including without limitation the rights to use, copy, modify, merge, 
+// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
+// to whom the Software is furnished to do so, subject to the following conditions:
+//
+//   The above copyright notice and this permission notice shall be included in all copies or 
+//   substantial portions of the Software.
+//
+//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+//   OR OTHER DEALINGS IN THE SOFTWARE.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module fdivsqrtpostproc(
+  input  logic clk, 
+  input  logic reset, 
+  input  logic DivStart, 
+  input logic [`DIVb+3:0] NextWSN, NextWCN, WS, WC,
+/*  input  logic XInfE, YInfE, 
+  input  logic XZeroE, YZeroE, 
+  input  logic XNaNE, YNaNE, 
+  input  logic XsE,
+  input  logic SqrtE,
+  input  logic SqrtM,
+  input  logic StallE,
+  input  logic StallM,*/
+  input logic [`DIVN-2:0]  D, // U0.N-1
+  input  logic [`DIVb+3:0] StickyWSA,
+  input  logic [`DURLEN-1:0] Dur,
+  input logic [`DIVb:0] LastSM,
+  input logic [`DIVb:0] FirstSM,
+  input logic [`DIVb-1:0] LastC,
+  input logic [`DIVb-1:0] FirstC,
+  input logic [`DIVCOPIES-1:0] qn,
+//  output logic [`DURLEN-1:0] EarlyTermShiftE,
+  output logic DivSE,
+//  output logic DivDone,
+  output logic NegSticky,
+  output logic DivBusy
+);
+  
+
+endmodule
\ No newline at end of file