Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

syntheses now write alib in their own directories

Browse Source
This commit is contained in:
Madeleine Masser-Frye 2022-07-09 02:40:41 +00:00
parent 853a3a5df1
commit 19db618b7f
2 changed files with 2 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
synthDC/Makefile
View File

@ -109,9 +109,9 @@ endif
dc_shell-xg-t -64bit -f scripts/$(NAME).tcl | tee $(OUTPUTDIR)/$(NAME).out
rm -rf $(OUTPUTDIR)/hdl
rm -rf $(OUTPUTDIR)/WORK
rm -rf $(OUTPUTDIR)/alib-52
clean:
rm -rf alib-52 analyzed
rm -f default.svf
rm -f command.log
rm -f filenames*.log

1
synthDC/scripts/synth.tcl
View File

@ -56,6 +56,7 @@ set vhdlout_show_unconnected_pins "true"
# Due to parameterized Verilog must use analyze/elaborate and not
# read_verilog/vhdl (change to pull in Verilog and/or VHDL)
#
set alib_library_analysis_path ./$outputDir
define_design_lib WORK -path ./$outputDir/WORK
analyze -f sverilog -lib WORK $my_verilog_files
elaborate $my_toplevel -lib WORK