Added wave config

added new signals to ILA.

fpga/constraints/debug2.xdc

@@ -651,3 +651,70 @@ create_debug_port u_ila_0 probe
 set_property port_width 12 [get_debug_ports u_ila_0/probe137]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe137]
 connect_debug_port u_ila_0/probe137 [get_nets [list {wallypipelinedsoc/uncore/plic.plic/intPending[1]} {wallypipelinedsoc/uncore/plic.plic/intPending[2]} {wallypipelinedsoc/uncore/plic.plic/intPending[3]} {wallypipelinedsoc/uncore/plic.plic/intPending[4]} {wallypipelinedsoc/uncore/plic.plic/intPending[5]} {wallypipelinedsoc/uncore/plic.plic/intPending[6]} {wallypipelinedsoc/uncore/plic.plic/intPending[7]} {wallypipelinedsoc/uncore/plic.plic/intPending[8]} {wallypipelinedsoc/uncore/plic.plic/intPending[9]} {wallypipelinedsoc/uncore/plic.plic/intPending[10]} {wallypipelinedsoc/uncore/plic.plic/intPending[11]} {wallypipelinedsoc/uncore/plic.plic/intPending[12]}]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 12 [get_debug_ports u_ila_0/probe138]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe138]
+connect_debug_port u_ila_0/probe138 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[0]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[1]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[2]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[3]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[4]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[5]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[6]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[7]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[8]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[9]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[10]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[11]}]]
+
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe139]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe139]
+connect_debug_port u_ila_0/probe139 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/MExtIntM}]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe140]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe140]
+connect_debug_port u_ila_0/probe140 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/SExtIntM} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe141]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe141]
+connect_debug_port u_ila_0/probe141 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/TimerIntM} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe142]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe142]
+connect_debug_port u_ila_0/probe142 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/SwIntM} ]]
+
+
+create_debug_port u_ila_0 probe
+set_property port_width 70 [get_debug_ports u_ila_0/probe143]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe143]
+connect_debug_port u_ila_0/probe143 [get_nets [list {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][10]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][10]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][10]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][10]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][10]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][10]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][10]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 3 [get_debug_ports u_ila_0/probe144]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe144]
+connect_debug_port u_ila_0/probe144 [get_nets [list {wallypipelinedsoc/uncore/plic.plic/intPriority[10][0]} {wallypipelinedsoc/uncore/plic.plic/intPriority[10][1]} {wallypipelinedsoc/uncore/plic.plic/intPriority[10][2]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 10 [get_debug_ports u_ila_0/probe145]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe145]
+connect_debug_port u_ila_0/probe145 [get_nets [list {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[1]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[2]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[3]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[4]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[5]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[6]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[7]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[8]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[9]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[10]} ]]
+
+
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe146]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe146]
+connect_debug_port u_ila_0/probe146 [get_nets [list {wallypipelinedsoc/uncore/clint.clint/MTIME[0]} {wallypipelinedsoc/uncore/clint.clint/MTIME[1]} {wallypipelinedsoc/uncore/clint.clint/MTIME[2]} {wallypipelinedsoc/uncore/clint.clint/MTIME[3]} {wallypipelinedsoc/uncore/clint.clint/MTIME[4]} {wallypipelinedsoc/uncore/clint.clint/MTIME[5]} {wallypipelinedsoc/uncore/clint.clint/MTIME[6]} {wallypipelinedsoc/uncore/clint.clint/MTIME[7]} {wallypipelinedsoc/uncore/clint.clint/MTIME[8]} {wallypipelinedsoc/uncore/clint.clint/MTIME[9]} {wallypipelinedsoc/uncore/clint.clint/MTIME[10]} {wallypipelinedsoc/uncore/clint.clint/MTIME[11]} {wallypipelinedsoc/uncore/clint.clint/MTIME[12]} {wallypipelinedsoc/uncore/clint.clint/MTIME[13]} {wallypipelinedsoc/uncore/clint.clint/MTIME[14]} {wallypipelinedsoc/uncore/clint.clint/MTIME[15]} {wallypipelinedsoc/uncore/clint.clint/MTIME[16]} {wallypipelinedsoc/uncore/clint.clint/MTIME[17]} {wallypipelinedsoc/uncore/clint.clint/MTIME[18]} {wallypipelinedsoc/uncore/clint.clint/MTIME[19]} {wallypipelinedsoc/uncore/clint.clint/MTIME[20]} {wallypipelinedsoc/uncore/clint.clint/MTIME[21]} {wallypipelinedsoc/uncore/clint.clint/MTIME[22]} {wallypipelinedsoc/uncore/clint.clint/MTIME[23]} {wallypipelinedsoc/uncore/clint.clint/MTIME[24]} {wallypipelinedsoc/uncore/clint.clint/MTIME[25]} {wallypipelinedsoc/uncore/clint.clint/MTIME[26]} {wallypipelinedsoc/uncore/clint.clint/MTIME[27]} {wallypipelinedsoc/uncore/clint.clint/MTIME[28]} {wallypipelinedsoc/uncore/clint.clint/MTIME[29]} {wallypipelinedsoc/uncore/clint.clint/MTIME[30]} {wallypipelinedsoc/uncore/clint.clint/MTIME[31]} {wallypipelinedsoc/uncore/clint.clint/MTIME[32]} {wallypipelinedsoc/uncore/clint.clint/MTIME[33]} {wallypipelinedsoc/uncore/clint.clint/MTIME[34]} {wallypipelinedsoc/uncore/clint.clint/MTIME[35]} {wallypipelinedsoc/uncore/clint.clint/MTIME[36]} {wallypipelinedsoc/uncore/clint.clint/MTIME[37]} {wallypipelinedsoc/uncore/clint.clint/MTIME[38]} {wallypipelinedsoc/uncore/clint.clint/MTIME[39]} {wallypipelinedsoc/uncore/clint.clint/MTIME[40]} {wallypipelinedsoc/uncore/clint.clint/MTIME[41]} {wallypipelinedsoc/uncore/clint.clint/MTIME[42]} {wallypipelinedsoc/uncore/clint.clint/MTIME[43]} {wallypipelinedsoc/uncore/clint.clint/MTIME[44]} {wallypipelinedsoc/uncore/clint.clint/MTIME[45]} {wallypipelinedsoc/uncore/clint.clint/MTIME[46]} {wallypipelinedsoc/uncore/clint.clint/MTIME[47]} {wallypipelinedsoc/uncore/clint.clint/MTIME[48]} {wallypipelinedsoc/uncore/clint.clint/MTIME[49]} {wallypipelinedsoc/uncore/clint.clint/MTIME[50]} {wallypipelinedsoc/uncore/clint.clint/MTIME[51]} {wallypipelinedsoc/uncore/clint.clint/MTIME[52]} {wallypipelinedsoc/uncore/clint.clint/MTIME[53]} {wallypipelinedsoc/uncore/clint.clint/MTIME[54]} {wallypipelinedsoc/uncore/clint.clint/MTIME[55]} {wallypipelinedsoc/uncore/clint.clint/MTIME[56]} {wallypipelinedsoc/uncore/clint.clint/MTIME[57]} {wallypipelinedsoc/uncore/clint.clint/MTIME[58]} {wallypipelinedsoc/uncore/clint.clint/MTIME[59]} {wallypipelinedsoc/uncore/clint.clint/MTIME[60]} {wallypipelinedsoc/uncore/clint.clint/MTIME[61]} {wallypipelinedsoc/uncore/clint.clint/MTIME[62]} {wallypipelinedsoc/uncore/clint.clint/MTIME[63]} ]]
+
+
+
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe147]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe147]
+connect_debug_port u_ila_0/probe147 [get_nets [list {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[0]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[1]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[2]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[3]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[4]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[5]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[6]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[7]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[8]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[9]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[10]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[11]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[12]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[13]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[14]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[15]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[16]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[17]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[18]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[19]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[20]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[21]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[22]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[23]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[24]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[25]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[26]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[27]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[28]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[29]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[30]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[31]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[32]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[33]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[34]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[35]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[36]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[37]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[38]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[39]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[40]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[41]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[42]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[43]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[44]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[45]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[46]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[47]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[48]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[49]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[50]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[51]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[52]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[53]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[54]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[55]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[56]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[57]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[58]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[59]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[60]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[61]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[62]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[63]} ]]
+
+
+
+create_debug_port u_ila_0 probe
+set_property port_width 12 [get_debug_ports u_ila_0/probe148]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe148]
+connect_debug_port u_ila_0/probe148 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[11]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe149]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe149]
+connect_debug_port u_ila_0/probe149 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[63]} ]]

fpga/generator/wave_config.wcfg

@@ -0,0 +1,345 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="/home/ross/repos/riscv-wally/fpga/generator/WallyFPGA.hw/hw_1/wave/hw_ila_data_1/hw_ila_data_1.wdb" id="1">
+         <top_modules>
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <zoom_setting>
+      <ZoomStartTime time="0fs"></ZoomStartTime>
+      <ZoomEndTime time="12980fs"></ZoomEndTime>
+      <Cursor1Time time="6221fs"></Cursor1Time>
+   </zoom_setting>
+   <column_width_setting>
+      <NameColumnWidth column_width="452"></NameColumnWidth>
+      <ValueColumnWidth column_width="149"></ValueColumnWidth>
+   </column_width_setting>
+   <WVObjectSize size="11" />
+   <wave_markers>
+   </wave_markers>
+   <wvobject type="array" fp_name="wallypipelinedsoc/core/PCM">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/core/PCM[63:0]</obj_property>
+      <obj_property name="ObjectShortName">PCM[63:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="wallypipelinedsoc/core/InstrM">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/core/InstrM[31:0]</obj_property>
+      <obj_property name="ObjectShortName">InstrM[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="wallypipelinedsoc/core/InstrValidM">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/core/InstrValidM</obj_property>
+      <obj_property name="ObjectShortName">InstrValidM</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="wallypipelinedsoc/core/TrapM">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/core/TrapM</obj_property>
+      <obj_property name="ObjectShortName">TrapM</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="group" fp_name="group468">
+      <obj_property name="label">CPU to LSU</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="isExpanded"></obj_property>
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/IEUAdrM">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/IEUAdrM[63:0]</obj_property>
+         <obj_property name="ObjectShortName">IEUAdrM[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/MemRWM">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/MemRWM[1:0]</obj_property>
+         <obj_property name="ObjectShortName">MemRWM[1:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/ReadDataM">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/ReadDataM[63:0]</obj_property>
+         <obj_property name="ObjectShortName">ReadDataM[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/lsu/WriteDataM">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/WriteDataM[63:0]</obj_property>
+         <obj_property name="ObjectShortName">WriteDataM[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject type="group" fp_name="group469">
+      <obj_property name="label">xIP</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="isExpanded"></obj_property>
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW_5">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW_5[9:9]</obj_property>
+         <obj_property name="ObjectShortName">MIP_REGW_5[9:9]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/trap/SIP_REGW">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/trap/SIP_REGW[9:9]</obj_property>
+         <obj_property name="ObjectShortName">SIP_REGW[9:9]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject type="group" fp_name="group470">
+      <obj_property name="label">PLIC</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="isExpanded"></obj_property>
+      <wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/requests">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/requests[12:1]</obj_property>
+         <obj_property name="ObjectShortName">requests[12:1]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/intPending">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/intPending[12:1]</obj_property>
+         <obj_property name="ObjectShortName">intPending[12:1]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/intInProgress">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/intInProgress[12:1]</obj_property>
+         <obj_property name="ObjectShortName">intInProgress[12:1]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject type="group" fp_name="group471">
+      <obj_property name="label">interrupts</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="isExpanded"></obj_property>
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/trap/MPendingIntsM">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/trap/MPendingIntsM[11:0]</obj_property>
+         <obj_property name="ObjectShortName">MPendingIntsM[11:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM[11:0]</obj_property>
+         <obj_property name="ObjectShortName">SPendingIntsM[11:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/InterruptM">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/InterruptM</obj_property>
+         <obj_property name="ObjectShortName">InterruptM</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject type="group" fp_name="group463">
+      <obj_property name="label">LSU to Bus</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="isExpanded"></obj_property>
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/lsu/LSUBusRead">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/LSUBusRead</obj_property>
+         <obj_property name="ObjectShortName">LSUBusRead</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/lsu/LSUBusWrite">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/LSUBusWrite</obj_property>
+         <obj_property name="ObjectShortName">LSUBusWrite</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/lsu/LSUBusAdr">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/LSUBusAdr[31:0]</obj_property>
+         <obj_property name="ObjectShortName">LSUBusAdr[31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/lsu/LSUBusSize">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/LSUBusSize[1:0]</obj_property>
+         <obj_property name="ObjectShortName">LSUBusSize[1:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/lsu/LSUBusHWDATA">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/LSUBusHWDATA[63:0]</obj_property>
+         <obj_property name="ObjectShortName">LSUBusHWDATA[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/lsu/LSUBusHRDATA">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/LSUBusHRDATA[63:0]</obj_property>
+         <obj_property name="ObjectShortName">LSUBusHRDATA[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/lsu/LSUBusAck">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/LSUBusAck</obj_property>
+         <obj_property name="ObjectShortName">LSUBusAck</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject type="group" fp_name="group488">
+      <obj_property name="label">xIE</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW_1">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW_1[1:1]</obj_property>
+         <obj_property name="ObjectShortName">MIE_REGW_1[1:1]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW_2">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW_2[3:3]</obj_property>
+         <obj_property name="ObjectShortName">MIE_REGW_2[3:3]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW_3">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW_3[5:5]</obj_property>
+         <obj_property name="ObjectShortName">MIE_REGW_3[5:5]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW_4">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW_4[7:7]</obj_property>
+         <obj_property name="ObjectShortName">MIE_REGW_4[7:7]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW_5">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW_5[9:9]</obj_property>
+         <obj_property name="ObjectShortName">MIE_REGW_5[9:9]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[11:11]</obj_property>
+         <obj_property name="ObjectShortName">MIE_REGW[11:11]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/trap/SIE_REGW">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/trap/SIE_REGW[9:9]</obj_property>
+         <obj_property name="ObjectShortName">SIE_REGW[9:9]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/trap/SIE_REGW_1">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/trap/SIE_REGW_1[1:1]</obj_property>
+         <obj_property name="ObjectShortName">SIE_REGW_1[1:1]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/trap/SIE_REGW_2">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/trap/SIE_REGW_2[5:5]</obj_property>
+         <obj_property name="ObjectShortName">SIE_REGW_2[5:5]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject type="group" fp_name="group487">
+      <obj_property name="label">sdc</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="isExpanded"></obj_property>
+      <wvobject type="logic" fp_name="wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_ERROR_Q">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_ERROR_Q</obj_property>
+         <obj_property name="ObjectShortName">r_DAT_ERROR_Q</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[4:0]</obj_property>
+         <obj_property name="ObjectShortName">r_curr_state[4:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/r_curr_state">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/r_curr_state[3:0]</obj_property>
+         <obj_property name="ObjectShortName">r_curr_state[3:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_clk_fsm/r_curr_state">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_clk_fsm/r_curr_state[3:0]</obj_property>
+         <obj_property name="ObjectShortName">r_curr_state[3:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/i_ERROR_CRC16">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/i_ERROR_CRC16</obj_property>
+         <obj_property name="ObjectShortName">i_ERROR_CRC16</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+   </wvobject>
+</wave_config>

pipelined/src/privileged/csri.sv

@@ -42,12 +42,12 @@ module csri #(parameter
     input logic 			CSRMWriteM, CSRSWriteM,
     input logic [`XLEN-1:0] CSRWriteValM,
     input logic [11:0] 		CSRAdrM,
-    input  logic             MExtIntM, SExtIntM, TimerIntM, SwIntM,
+    (* mark_debug = "true" *)    input logic MExtIntM, SExtIntM, TimerIntM, SwIntM,
     input logic [11:0] 		MIDELEG_REGW,
     output logic [11:0] 	MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW
   );
 
-  logic [11:0]     IP_REGW_writeable; // only SEIP, STIP, SSIP are actually writeable; the rest are hardwired to 0
+  (* mark_debug = "true" *) logic [11:0]     IP_REGW_writeable; // only SEIP, STIP, SSIP are actually writeable; the rest are hardwired to 0
   logic [11:0]     IP_REGW, IE_REGW;
   logic [11:0]     MIP_WRITE_MASK, SIP_WRITE_MASK, MIE_WRITE_MASK;
   logic            WriteMIPM, WriteMIEM, WriteSIPM, WriteSIEM;

pipelined/src/privileged/csrm.sv

@@ -78,8 +78,8 @@ module csrm #(parameter
     output logic [`XLEN-1:0] CSRMReadValM, MTVEC_REGW,
     (* mark_debug = "true" *)  output logic [`XLEN-1:0] MEPC_REGW,    
     output logic [31:0]      MCOUNTEREN_REGW, MCOUNTINHIBIT_REGW, 
-    output logic [`XLEN-1:0] MEDELEG_REGW,
+(* mark_debug = "true" *)      output logic [`XLEN-1:0] MEDELEG_REGW,
-    output logic [11:0]      MIDELEG_REGW,
+(* mark_debug = "true" *)      output logic [11:0]      MIDELEG_REGW,
     // 64-bit registers in RV64, or two 32-bit registers in RV32
     //output var logic [63:0]      PMPCFG_ARRAY_REGW[`PMP_ENTRIES/8-1:0],
     output 		     var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],

pipelined/src/uncore/clint.sv

@@ -42,7 +42,7 @@ module clint (
   input logic [1:0] 	   HTRANS,
   output logic [`XLEN-1:0] HREADCLINT,
   output logic 			   HRESPCLINT, HREADYCLINT,
-  output logic [63:0]      MTIME, 
+  (* mark_debug = "true" *) output logic [63:0] MTIME, 
   output logic 			   TimerIntM, SwIntM);
 
   logic        MSIP;
@@ -50,7 +50,7 @@ module clint (
   logic [15:0] entry, entryd;
   logic memwrite;
   logic initTrans;
-  logic [63:0] MTIMECMP;
+  (* mark_debug = "true" *)    logic [63:0] MTIMECMP;
   logic [`XLEN/8-1:0] ByteMaskM;
   integer             i;
 

pipelined/src/uncore/plic.sv

@@ -70,9 +70,9 @@ module plic (
   
   // context-dependent signals
   logic [`C-1:0][2:0]       intThreshold;
-  logic [`C-1:0][`N:1]      intEn;
+    (* mark_debug = "true" *)  logic [`C-1:0][`N:1]      intEn;
   logic [`C-1:0][5:0]       intClaim; // ID's are 6 bits if we stay within 63 sources
-  logic [`C-1:0][7:1][`N:1] irqMatrix;
+    (* mark_debug = "true" *)  logic [`C-1:0][7:1][`N:1] irqMatrix;
   logic [`C-1:0][7:1]       priorities_with_irqs;
   logic [`C-1:0][7:1]       max_priority_with_irqs;
   logic [`C-1:0][`N:1]      irqs_at_max_priority;