diff --git a/pipelined/src/generic/flop/bram.sv b/pipelined/src/generic/flop/bram.sv
deleted file mode 100644
index 75fb76635..000000000
--- a/pipelined/src/generic/flop/bram.sv
+++ /dev/null
@@ -1,47 +0,0 @@
-// This model actually works correctly with vivado.
-
-
-module bram2p1r1w
-  #(
-	//--------------------------------------------------------------------------
-	parameter NUM_COL = 8,
-	parameter COL_WIDTH = 8,
-	parameter ADDR_WIDTH = 10,
-	// Addr Width in bits : 2 *ADDR_WIDTH = RAM Depth
-	parameter DATA_WIDTH = NUM_COL*COL_WIDTH // Data Width in bits
-	//----------------------------------------------------------------------
-	) (
-	   input logic 					 clk,
-	   input logic 					 enaA,
-	   input logic [ADDR_WIDTH-1:0]  addrA,
-	   output logic [DATA_WIDTH-1:0] doutA,
-	   input logic 					 enaB,
-	   input logic [NUM_COL-1:0] 	 weB,
-	   input logic [ADDR_WIDTH-1:0]  addrB,
-	   input logic [DATA_WIDTH-1:0]  dinB
-	   );
-  // Core Memory
-  logic [DATA_WIDTH-1:0] 			 RAM [(2**ADDR_WIDTH)-1:0];
-  integer 							 i;
-
-  initial begin
-	$readmemh("big64.txt", RAM);
-  end
-
-  // Port-A Operation
-  always @ (posedge clk) begin
-	if(enaA) begin
-	  doutA <= RAM[addrA];
-	end
-  end
-  // Port-B Operation:
-  always @ (posedge clk) begin
-	if(enaB) begin
-	  for(i=0;i<NUM_COL;i=i+1) begin
-		if(weB[i]) begin
-		  RAM[addrB][i*COL_WIDTH +: COL_WIDTH] <= dinB[i*COL_WIDTH +:COL_WIDTH];
-		end
-	  end
-	end
-  end
-endmodule // bytewrite_tdp_ram_rf
diff --git a/pipelined/src/generic/flop/simpleram.sv b/pipelined/src/generic/flop/simpleram.sv
index 42411f977..a05f8dc40 100644
--- a/pipelined/src/generic/flop/simpleram.sv
+++ b/pipelined/src/generic/flop/simpleram.sv
@@ -39,6 +39,14 @@ module simpleram #(parameter BASE=0, RANGE = 65535) (
   output logic [`XLEN-1:0] rd
 );
 
+  localparam ADDR_WDITH = $clog2(RANGE/8);
+  localparam OFFSET = $clog2(`XLEN/8);
+
+
+  bram1p1rw #(`XLEN/8, 8, ADDR_WDITH) 
+  memory(.clk, .ena(we), .we(ByteMask), .addr(a[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(rd), .din(wd));
+  
+/* -----\/----- EXCLUDED -----\/-----
   logic [`XLEN-1:0] RAM[BASE>>(1+`XLEN/32):(RANGE+BASE)>>1+(`XLEN/32)];
   
   // discard bottom 2 or 3 bits of address offset within word or doubleword
@@ -55,5 +63,6 @@ module simpleram #(parameter BASE=0, RANGE = 65535) (
       if (we & ByteMask[index]) RAM[adrmsbs][8*(index+1)-1:8*index] <= #1 wd[8*(index+1)-1:8*index];
     end
   end
+ -----/\----- EXCLUDED -----/\----- */
 endmodule
 
diff --git a/pipelined/src/lsu/dtim.sv b/pipelined/src/lsu/dtim.sv
index 6ca5be4a6..5b4969ab8 100644
--- a/pipelined/src/lsu/dtim.sv
+++ b/pipelined/src/lsu/dtim.sv
@@ -48,7 +48,7 @@ module dtim(
   output logic              DCacheCommittedM,
   output logic              DCacheMiss,
   output logic              DCacheAccess);
-
+  
   simpleram #(.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram (
       .clk, .ByteMask(ByteMaskM),
       .a(CPUBusy | LSURWM[0] | reset ? IEUAdrM[31:0] : IEUAdrE[31:0]), // move mux out; this shouldn't be needed when stails are handled differently ***
diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv
index 105493399..2b8e6df8b 100644
--- a/pipelined/testbench/testbench.sv
+++ b/pipelined/testbench/testbench.sv
@@ -187,9 +187,9 @@ logic [3:0] dummy;
         pathname = tvpaths[0];
       else pathname = tvpaths[1]; */
       memfilename = {pathname, tests[test], ".elf.memfile"};
-      if (`IMEM == `MEM_TIM) $readmemh(memfilename, dut.core.ifu.irom.irom.ram.RAM);
+      if (`IMEM == `MEM_TIM) $readmemh(memfilename, dut.core.ifu.irom.irom.ram.memory.RAM);
       else              $readmemh(memfilename, dut.uncore.ram.ram.memory.RAM);
-      if (`DMEM == `MEM_TIM) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
+      if (`DMEM == `MEM_TIM) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.memory.RAM);
 
       ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
       ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
@@ -248,7 +248,7 @@ logic [3:0] dummy;
         /* verilator lint_off INFINITELOOP */
         while (signature[i] !== 'bx) begin
           logic [`XLEN-1:0] sig;
-          if (`DMEM == `MEM_TIM) sig = dut.core.lsu.dtim.dtim.ram.RAM[testadr+i];
+          if (`DMEM == `MEM_TIM) sig = dut.core.lsu.dtim.dtim.ram.memory.RAM[testadrNoBase+i];
           else                   sig = dut.uncore.ram.ram.memory.RAM[testadrNoBase+i];
           //$display("signature[%h] = %h sig = %h", i, signature[i], sig);
           if (signature[i] !== sig &
@@ -286,9 +286,9 @@ logic [3:0] dummy;
             //pathname = tvpaths[tests[0]];
             memfilename = {pathname, tests[test], ".elf.memfile"};
             //$readmemh(memfilename, dut.uncore.ram.ram.memory.RAM);
-            if (`IMEM == `MEM_TIM) $readmemh(memfilename, dut.core.ifu.irom.irom.ram.RAM);
+            if (`IMEM == `MEM_TIM) $readmemh(memfilename, dut.core.ifu.irom.irom.ram.memory.RAM);
             else                   $readmemh(memfilename, dut.uncore.ram.ram.memory.RAM);
-            if (`DMEM == `MEM_TIM) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
+            if (`DMEM == `MEM_TIM) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.memory.RAM);
 
             ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
             ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};