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working GPIO interrupt demo

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bbracker 2021-04-15 21:09:15 -04:00
parent 76f50d7a69
commit 195cead01c
10 changed files with 147 additions and 414 deletions
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3
wally-pipelined/config/rv32ic/wally-config.vh
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@ -90,7 +90,8 @@
`define UART_PRESCALE 1 `define UART_PRESCALE 1
// Interrupt configuration // Interrupt configuration
`define PLIC_NUM_SRC 53 `define PLIC_NUM_SRC 4
`define PLIC_GPIO_ID 3
`define PLIC_UART_ID 4 `define PLIC_UART_ID 4
/* verilator lint_off STMTDLY */ /* verilator lint_off STMTDLY */

3
wally-pipelined/config/rv64ic/wally-config.vh
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@ -82,7 +82,7 @@
// Test modes // Test modes
// Tie GPIO outputs back to inputs // Tie GPIO outputs back to inputs
`define GPIO_LOOPBACK_TEST 0 `define GPIO_LOOPBACK_TEST 1
// Busybear special CSR config to match OVPSim // Busybear special CSR config to match OVPSim
`define OVPSIM_CSR_CONFIG 0 `define OVPSIM_CSR_CONFIG 0
@ -92,6 +92,7 @@
// Interrupt configuration // Interrupt configuration
`define PLIC_NUM_SRC 4 `define PLIC_NUM_SRC 4
`define PLIC_GPIO_ID 3
`define PLIC_UART_ID 4 `define PLIC_UART_ID 4
/* verilator lint_off STMTDLY */ /* verilator lint_off STMTDLY */

8
wally-pipelined/regression/wave-dos/peripheral-waves.do
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@ -58,14 +58,16 @@ add wave -divider
add wave -divider add wave -divider
# peripherals # peripherals
add wave -hex /testbench/dut/hart/ebu/* add wave -hex /testbench/dut/uncore/gpio/*
add wave -divider
add wave -hex /testbench/dut/uncore/uart/u/*
add wave -divider add wave -divider
add wave -hex /testbench/dut/uncore/plic/* add wave -hex /testbench/dut/uncore/plic/*
add wave -hex /testbench/dut/uncore/plic/intPriority add wave -hex /testbench/dut/uncore/plic/intPriority
add wave -hex /testbench/dut/uncore/plic/pendingArray add wave -hex /testbench/dut/uncore/plic/pendingArray
add wave -divider add wave -divider
add wave -hex /testbench/dut/uncore/uart/u/*
add wave -divider
add wave -hex /testbench/dut/hart/ebu/*
add wave -divider
add wave -divider add wave -divider
# everything else # everything else

6
wally-pipelined/src/ebu/ahblite.sv
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@ -49,7 +49,6 @@ module ahblite (
// Signals from MMU // Signals from MMU
input logic [`XLEN-1:0] MMUPAdr, input logic [`XLEN-1:0] MMUPAdr,
input logic MMUTranslate, MMUTranslationComplete, input logic MMUTranslate, MMUTranslationComplete,
input logic TrapM,
output logic [`XLEN-1:0] MMUReadPTE, output logic [`XLEN-1:0] MMUReadPTE,
output logic MMUReady, output logic MMUReady,
// Return from bus // Return from bus
@ -131,6 +130,7 @@ module ahblite (
else NextBusState = IDLE; // if (InstrReadF still high) else NextBusState = IDLE; // if (InstrReadF still high)
INSTRREADC: if (~HREADY) NextBusState = INSTRREADC; // "C" for "competing", meaning please don't mess up the memread in the W stage. INSTRREADC: if (~HREADY) NextBusState = INSTRREADC; // "C" for "competing", meaning please don't mess up the memread in the W stage.
else NextBusState = IDLE; else NextBusState = IDLE;
default: NextBusState = IDLE;
endcase endcase
// stall signals // stall signals
@ -138,11 +138,11 @@ module ahblite (
// since translation might not be complete. // since translation might not be complete.
assign #2 DataStall = ((NextBusState == MEMREAD) || (NextBusState == MEMWRITE) || assign #2 DataStall = ((NextBusState == MEMREAD) || (NextBusState == MEMWRITE) ||
(NextBusState == ATOMICREAD) || (NextBusState == ATOMICWRITE) || (NextBusState == ATOMICREAD) || (NextBusState == ATOMICWRITE) ||
(NextBusState == MMUTRANSLATE) || (MMUTranslate && ~MMUTranslationComplete)); // && ~TrapM (NextBusState == MMUTRANSLATE) || (MMUTranslate && ~MMUTranslationComplete));
// *** Could get finer grained stalling if we distinguish between MMU // *** Could get finer grained stalling if we distinguish between MMU
// instruction address translation and data address translation // instruction address translation and data address translation
assign #1 InstrStall = ((NextBusState == INSTRREAD) || (NextBusState == INSTRREADC) || assign #1 InstrStall = ((NextBusState == INSTRREAD) || (NextBusState == INSTRREADC) ||
(NextBusState == MMUTRANSLATE) || (MMUTranslate && ~MMUTranslationComplete)); // && ~TrapM (NextBusState == MMUTRANSLATE) || (MMUTranslate && ~MMUTranslationComplete));
// bus outputs // bus outputs
assign #1 GrantData = (NextBusState == MEMREAD) || (NextBusState == MEMWRITE) || assign #1 GrantData = (NextBusState == MEMREAD) || (NextBusState == MEMWRITE) ||

190
wally-pipelined/src/uncore/gpio.sv
View File

@ -2,7 +2,7 @@
// gpio.sv // gpio.sv
// //
// Written: David_Harris@hmc.edu 14 January 2021 // Written: David_Harris@hmc.edu 14 January 2021
// Modified: // Modified: bbracker@hmc.edu 15 Apr. 2021
// //
// Purpose: General Purpose I/O peripheral // Purpose: General Purpose I/O peripheral
// See FE310-G002-Manual-v19p05 for specifications // See FE310-G002-Manual-v19p05 for specifications
@ -38,84 +38,134 @@ module gpio (
output logic [`XLEN-1:0] HREADGPIO, output logic [`XLEN-1:0] HREADGPIO,
output logic HRESPGPIO, HREADYGPIO, output logic HRESPGPIO, HREADYGPIO,
input logic [31:0] GPIOPinsIn, input logic [31:0] GPIOPinsIn,
output logic [31:0] GPIOPinsOut, GPIOPinsEn); output logic [31:0] GPIOPinsOut, GPIOPinsEn,
output logic GPIOIntr);
logic [31:0] INPUT_VAL, INPUT_EN, OUTPUT_EN, OUTPUT_VAL; logic [31:0] input0d, input1d, input2d, input3d;
logic [31:0] input_val, input_en, output_en, output_val;
logic [7:0] entry, HADDRd; logic [31:0] rise_ie, rise_ip, fall_ie, fall_ip, high_ie, high_ip, low_ie, low_ip;
logic initTrans, memread, memwrite;
logic initTrans, memread, memwrite;
logic [7:0] entry, entryd, HADDRd;
logic [31:0] Din, Dout;
// AHB I/O
assign entry = {HADDR[7:2],2'b0};
assign initTrans = HREADY & HSELGPIO & (HTRANS != 2'b00); assign initTrans = HREADY & HSELGPIO & (HTRANS != 2'b00);
assign memread = initTrans & ~HWRITE;
// Control Signals // entryd and memwrite are delayed by a cycle because AHB controller waits a cycle before outputting write data
flopenr #(1) memreadreg(HCLK, ~HRESETn, initTrans, ~HWRITE, memread); flopr #(1) memwriteflop(HCLK, ~HRESETn, initTrans & HWRITE, memwrite);
flopenr #(1) memwritereg(HCLK, ~HRESETn, initTrans, HWRITE, memwrite); flopr #(8) entrydflop(HCLK, ~HRESETn, entry, entryd);
flopenr #(8) haddrreg(HCLK, ~HRESETn, initTrans, HADDR, HADDRd);
// Response Signals
assign HRESPGPIO = 0; // OK assign HRESPGPIO = 0; // OK
assign HREADYGPIO = 1; // never ask for wait states assign HREADYGPIO = 1'b1; // GPIO never takes >1 cycle to respond
// word aligned reads
generate
if (`XLEN==64)
assign #2 entry = {HADDR[7:3], 3'b000};
else
assign #2 entry = {HADDR[7:2], 2'b00};
endgenerate
generate
if (`GPIO_LOOPBACK_TEST) // connect OUT to IN for loopback testing
assign INPUT_VAL = GPIOPinsOut & INPUT_EN & OUTPUT_EN;
else
assign INPUT_VAL = GPIOPinsIn & INPUT_EN;
endgenerate
assign GPIOPinsOut = OUTPUT_VAL;
assign GPIOPinsEn = OUTPUT_EN;
// register access // account for subword read/write circuitry
// -- Note GPIO registers are 32 bits no matter what; access them with LW SW.
// (At least that's what I think when FE310 spec says "only naturally aligned 32-bit accesses are supported")
generate generate
if (`XLEN==64) begin if (`XLEN == 64) begin
always_ff @(posedge HCLK) begin always_comb
case(entry) if (entryd[2]) begin
8'h00: HREADGPIO <= {INPUT_EN, INPUT_VAL}; Din = HWDATA[63:32];
8'h08: HREADGPIO <= {OUTPUT_VAL, OUTPUT_EN}; HREADGPIO = {Dout,32'b0};
8'h40: HREADGPIO <= 0; // OUT_XOR reads as 0 end else begin
default: HREADGPIO <= 0; Din = HWDATA[31:0];
endcase HREADGPIO = {32'b0,Dout};
end
always_ff @(posedge HCLK or negedge HRESETn)
if (~HRESETn) begin
INPUT_EN <= 0;
OUTPUT_EN <= 0;
OUTPUT_VAL <= 0; // spec indicates synchronous reset (software control)
end else if (memwrite) begin
if (entry == 8'h00) INPUT_EN <= HWDATA[63:32];
if (entry == 8'h08) {OUTPUT_VAL, OUTPUT_EN} <= HWDATA;
if (entry == 8'h40) OUTPUT_VAL <= OUTPUT_VAL ^ HWDATA[31:0]; // OUT_XOR
end end
end else begin // 32-bit end else begin // 32-bit
always_ff @(posedge HCLK) begin always_comb begin
case(entry) Din = HWDATA[31:0];
8'h00: HREADGPIO <= INPUT_VAL; HREADGPIO = Dout;
8'h04: HREADGPIO <= INPUT_EN; end
8'h08: HREADGPIO <= OUTPUT_EN;
8'h0C: HREADGPIO <= OUTPUT_VAL;
8'h40: HREADGPIO <= 0; // OUT_XOR reads as 0
default: HREADGPIO <= 0;
endcase
end
always_ff @(posedge HCLK or negedge HRESETn)
if (~HRESETn) begin
INPUT_EN <= 0;
OUTPUT_EN <= 0;
end else if (memwrite) begin
if (entry == 8'h04) INPUT_EN <= HWDATA;
if (entry == 8'h08) OUTPUT_EN <= HWDATA;
if (entry == 8'h0C) OUTPUT_VAL <= HWDATA;
if (entry == 8'h40) OUTPUT_VAL <= OUTPUT_VAL ^ HWDATA; // OUT_XOR
end
end end
endgenerate endgenerate
// register access
always_ff @(posedge HCLK, negedge HRESETn) begin
// reads
case(entry)
8'h00: Dout <= #1 input_val;
8'h04: Dout <= #1 input_en;
8'h08: Dout <= #1 output_en;
8'h0C: Dout <= #1 output_val;
8'h18: Dout <= #1 rise_ie;
8'h1C: Dout <= #1 rise_ip;
8'h20: Dout <= #1 fall_ie;
8'h24: Dout <= #1 fall_ip;
8'h28: Dout <= #1 high_ie;
8'h2C: Dout <= #1 high_ip;
8'h30: Dout <= #1 low_ie;
8'h34: Dout <= #1 low_ip;
8'h40: Dout <= #1 0; // OUT_XOR reads as 0
default: Dout <= #1 0;
endcase
// writes
if (~HRESETn) begin
// asynch reset
input_en <= 0;
output_en <= 0;
// *** synch reset not yet implemented
output_val <= #1 0;
rise_ie <= #1 0;
rise_ip <= #1 0;
fall_ie <= #1 0;
fall_ip <= #1 0;
high_ie <= #1 0;
high_ip <= #1 0;
low_ie <= #1 0;
low_ip <= #1 0;
end else if (memwrite)
// According to FE310 spec: Once the interrupt is pending, it will remain set until a 1 is written to the *_ip register at that bit.
case(entryd)
8'h04: input_en <= #1 Din;
8'h08: output_en <= #1 Din;
8'h0C: output_val <= #1 Din;
8'h18: rise_ie <= #1 Din;
8'h1C: rise_ip <= #1 rise_ip & ~Din;
8'h20: fall_ie <= #1 Din;
8'h24: fall_ip <= #1 fall_ip & ~Din;
8'h28: high_ie <= #1 Din;
8'h2C: high_ip <= #1 high_ip & ~Din;
8'h30: low_ie <= #1 Din;
8'h34: low_ip <= #1 low_ip & ~Din;
8'h40: output_val <= #1 output_val ^ Din; // OUT_XOR
endcase
end
// chip i/o
generate
if (`GPIO_LOOPBACK_TEST) // connect OUT to IN for loopback testing
assign input0d = GPIOPinsOut & input_en & output_en;
else
assign input0d = GPIOPinsIn & input_en;
endgenerate
// *** this costs lots of flops; I suspect they don't need to be resettable, do they?
flop #(32) sync1(HCLK,input0d,input1d);
flop #(32) sync2(HCLK,input1d,input2d);
flop #(32) sync3(HCLK,input2d,input3d);
assign input_val = input3d;
assign GPIOPinsOut = output_val;
assign GPIOPinsEn = output_en;
// interrupts
always_ff @(posedge HCLK) begin
if (memwrite && (entryd == 8'h1C))
rise_ip <= rise_ip & ~Din | (input2d & ~input3d);
else
rise_ip <= rise_ip | (input2d & ~input3d);
if (memwrite && (entryd == 8'h24))
fall_ip <= fall_ip & ~Din | (~input2d & input3d);
else
fall_ip <= fall_ip | (~input2d & input3d);
if (memwrite && (entryd == 8'h2C))
high_ip <= high_ip & ~Din | input3d;
else
high_ip <= high_ip | input3d;
if (memwrite && (entryd == 8'h34))
low_ip <= low_ip & ~Din | ~input3d;
else
low_ip <= low_ip | ~input3d;
end
assign GPIOIntr = |{(rise_ip & rise_ie),(fall_ip & fall_ip),(high_ip & high_ie),(low_ip & low_ie)};
endmodule endmodule

20
wally-pipelined/src/uncore/plic.sv
View File

@ -37,12 +37,12 @@
module plic ( module plic (
input logic HCLK, HRESETn, input logic HCLK, HRESETn,
input logic HSELPLIC, input logic HSELPLIC,
input logic [27:0] HADDR, input logic [27:0] HADDR, // *** could factor out entryd into HADDRd at the level of uncore
input logic HWRITE, input logic HWRITE,
input logic HREADY, input logic HREADY,
input logic [1:0] HTRANS, input logic [1:0] HTRANS,
input logic [`XLEN-1:0] HWDATA, input logic [`XLEN-1:0] HWDATA,
input logic UARTIntr, input logic UARTIntr,GPIOIntr,
output logic [`XLEN-1:0] HREADPLIC, output logic [`XLEN-1:0] HREADPLIC,
output logic HRESPPLIC, HREADYPLIC, output logic HRESPPLIC, HREADYPLIC,
output logic ExtIntM); output logic ExtIntM);
@ -77,7 +77,7 @@ module plic (
// account for subword read/write circuitry // account for subword read/write circuitry
// -- Note PLIC registers are 32 bits no matter what; access them with LW SW. // -- Note PLIC registers are 32 bits no matter what; access them with LW SW.
generate generate // *** add ld, sd functionality
if (`XLEN == 64) begin if (`XLEN == 64) begin
always_comb always_comb
if (entryd[2]) begin if (entryd[2]) begin
@ -162,11 +162,15 @@ module plic (
endgenerate endgenerate
// connect sources to requests // connect sources to requests
`ifdef PLIC_UART_ID always_comb begin
assign requests[`PLIC_UART_ID] = UARTIntr; requests = {N{1'b0}};
`endif `ifdef PLIC_GPIO_ID
// or temporarily connect them to nothing requests[`PLIC_GPIO_ID] = GPIOIntr;
assign requests[3:1] = 3'b0; `endif
`ifdef PLIC_UART_ID
requests[`PLIC_UART_ID] = UARTIntr;
`endif
end
// pending updates // pending updates
// *** verify that this matches the expectations of the things that make requests (in terms of timing, edge-triggered vs level-triggered) // *** verify that this matches the expectations of the things that make requests (in terms of timing, edge-triggered vs level-triggered)

325
wally-pipelined/src/uncore/plic_temp.sv
View File

@ -1,325 +0,0 @@
///////////////////////////////////////////
// plic_temp.sv
//
// This was made to provide a register interface to busybear. I think we'll end up replacing it with our more configurable plic.
//
// Written: bbracker@hmc.edu 18 January 2021
// Modified:
//
// Purpose: Platform-Level Interrupt Controller
// See FU540-C000-Manual-v1p0 for specifications
// *** we might want to add support for FE310-G002-Manual-v19p05 version
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-config.vh"
module plic_temp (
input logic HCLK, HRESETn,
input logic HSELPLIC,
input logic [27:0] HADDR,
input logic HWRITE,
input logic [`XLEN-1:0] HWDATA,
output logic [`XLEN-1:0] HREADPLIC,
output logic HRESPPLIC, HREADYPLIC);
logic memread, memwrite;
parameter numSrc = 53;
logic [2:0] intPriority [numSrc:1];
logic [2:0] intThreshold;
logic [numSrc:1] intPending, intEn;
logic [31:0] intClaim;
logic [27:0] entry;
// AHB I/O
assign memread = HSELPLIC & ~HWRITE;
assign memwrite = HSELPLIC & HWRITE;
assign HRESPPLIC = 0; // OK
assign HREADYPLIC = 1'b1; // will need to be modified if PLIC ever needs more than 1 cycle to do something
// word aligned reads
generate
if (`XLEN==64)
assign #2 entry = {HADDR[15:3], 3'b000};
else
assign #2 entry = {HADDR[15:2], 2'b00};
endgenerate
// register access
generate
if (`XLEN==64) begin
always @(posedge HCLK) begin
// reading
case(entry)
// priority assignments
28'hc000004: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[1]};
28'hc000008: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[2]};
28'hc00000c: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[3]};
28'hc000010: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[4]};
28'hc000014: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[5]};
28'hc000018: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[6]};
28'hc00001c: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[7]};
28'hc000020: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[8]};
28'hc000024: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[9]};
28'hc000028: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[10]};
28'hc00002c: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[11]};
28'hc000030: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[12]};
28'hc000034: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[13]};
28'hc000038: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[14]};
28'hc00003c: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[15]};
28'hc000040: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[16]};
28'hc000044: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[17]};
28'hc000048: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[18]};
28'hc00004c: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[19]};
28'hc000050: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[20]};
28'hc000054: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[21]};
28'hc000058: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[22]};
28'hc00005c: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[23]};
28'hc000060: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[24]};
28'hc000064: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[25]};
28'hc000068: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[26]};
28'hc00006c: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[27]};
28'hc000070: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[28]};
28'hc000074: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[29]};
28'hc000078: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[30]};
28'hc00007c: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[31]};
28'hc000080: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[32]};
28'hc000084: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[33]};
28'hc000088: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[34]};
28'hc00008c: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[35]};
28'hc000090: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[36]};
28'hc000094: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[37]};
28'hc000098: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[38]};
28'hc00009c: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[39]};
28'hc0000a0: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[40]};
28'hc0000a4: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[41]};
28'hc0000a8: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[42]};
28'hc0000ac: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[43]};
28'hc0000b0: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[44]};
28'hc0000b4: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[45]};
28'hc0000b8: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[46]};
28'hc0000bc: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[47]};
28'hc0000c0: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[48]};
28'hc0000c4: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[49]};
28'hc0000c8: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[50]};
28'hc0000cc: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[51]};
28'hc0000d0: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[52]};
28'hc0000d4: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[53]};
// hart 0 configurations
28'hc001000: HREADPLIC <= {{(`XLEN-32){1'b0}},intPending[31:1],1'b0};
28'hc001004: HREADPLIC <= {{(`XLEN-22){1'b0}},intPending[53:32]};
28'hc002000: HREADPLIC <= {{(`XLEN-32){1'b0}},intEn[31:1],1'b0};
28'hc002004: HREADPLIC <= {{(`XLEN-22){1'b0}},intEn[53:32]};
28'hc200000: HREADPLIC <= {{(`XLEN-3){1'b0}},intThreshold[2:0]};
28'hc200004: HREADPLIC <= {{(`XLEN-32){1'b0}},intClaim[31:0]};
default: HREADPLIC <= 0;
endcase
// writing
case(entry)
// priority assignments
28'hc000004: if (memwrite) intPriority[1] <= HWDATA[2:0];
28'hc000008: if (memwrite) intPriority[2] <= HWDATA[2:0];
28'hc00000c: if (memwrite) intPriority[3] <= HWDATA[2:0];
28'hc000010: if (memwrite) intPriority[4] <= HWDATA[2:0];
28'hc000014: if (memwrite) intPriority[5] <= HWDATA[2:0];
28'hc000018: if (memwrite) intPriority[6] <= HWDATA[2:0];
28'hc00001c: if (memwrite) intPriority[7] <= HWDATA[2:0];
28'hc000020: if (memwrite) intPriority[8] <= HWDATA[2:0];
28'hc000024: if (memwrite) intPriority[9] <= HWDATA[2:0];
28'hc000028: if (memwrite) intPriority[10] <= HWDATA[2:0];
28'hc00002c: if (memwrite) intPriority[11] <= HWDATA[2:0];
28'hc000030: if (memwrite) intPriority[12] <= HWDATA[2:0];
28'hc000034: if (memwrite) intPriority[13] <= HWDATA[2:0];
28'hc000038: if (memwrite) intPriority[14] <= HWDATA[2:0];
28'hc00003c: if (memwrite) intPriority[15] <= HWDATA[2:0];
28'hc000040: if (memwrite) intPriority[16] <= HWDATA[2:0];
28'hc000044: if (memwrite) intPriority[17] <= HWDATA[2:0];
28'hc000048: if (memwrite) intPriority[18] <= HWDATA[2:0];
28'hc00004c: if (memwrite) intPriority[19] <= HWDATA[2:0];
28'hc000050: if (memwrite) intPriority[20] <= HWDATA[2:0];
28'hc000054: if (memwrite) intPriority[21] <= HWDATA[2:0];
28'hc000058: if (memwrite) intPriority[22] <= HWDATA[2:0];
28'hc00005c: if (memwrite) intPriority[23] <= HWDATA[2:0];
28'hc000060: if (memwrite) intPriority[24] <= HWDATA[2:0];
28'hc000064: if (memwrite) intPriority[25] <= HWDATA[2:0];
28'hc000068: if (memwrite) intPriority[26] <= HWDATA[2:0];
28'hc00006c: if (memwrite) intPriority[27] <= HWDATA[2:0];
28'hc000070: if (memwrite) intPriority[28] <= HWDATA[2:0];
28'hc000074: if (memwrite) intPriority[29] <= HWDATA[2:0];
28'hc000078: if (memwrite) intPriority[30] <= HWDATA[2:0];
28'hc00007c: if (memwrite) intPriority[31] <= HWDATA[2:0];
28'hc000080: if (memwrite) intPriority[32] <= HWDATA[2:0];
28'hc000084: if (memwrite) intPriority[33] <= HWDATA[2:0];
28'hc000088: if (memwrite) intPriority[34] <= HWDATA[2:0];
28'hc00008c: if (memwrite) intPriority[35] <= HWDATA[2:0];
28'hc000090: if (memwrite) intPriority[36] <= HWDATA[2:0];
28'hc000094: if (memwrite) intPriority[37] <= HWDATA[2:0];
28'hc000098: if (memwrite) intPriority[38] <= HWDATA[2:0];
28'hc00009c: if (memwrite) intPriority[39] <= HWDATA[2:0];
28'hc0000a0: if (memwrite) intPriority[40] <= HWDATA[2:0];
28'hc0000a4: if (memwrite) intPriority[41] <= HWDATA[2:0];
28'hc0000a8: if (memwrite) intPriority[42] <= HWDATA[2:0];
28'hc0000ac: if (memwrite) intPriority[43] <= HWDATA[2:0];
28'hc0000b0: if (memwrite) intPriority[44] <= HWDATA[2:0];
28'hc0000b4: if (memwrite) intPriority[45] <= HWDATA[2:0];
28'hc0000b8: if (memwrite) intPriority[46] <= HWDATA[2:0];
28'hc0000bc: if (memwrite) intPriority[47] <= HWDATA[2:0];
28'hc0000c0: if (memwrite) intPriority[48] <= HWDATA[2:0];
28'hc0000c4: if (memwrite) intPriority[49] <= HWDATA[2:0];
28'hc0000c8: if (memwrite) intPriority[50] <= HWDATA[2:0];
28'hc0000cc: if (memwrite) intPriority[51] <= HWDATA[2:0];
28'hc0000d0: if (memwrite) intPriority[52] <= HWDATA[2:0];
28'hc0000d4: if (memwrite) intPriority[53] <= HWDATA[2:0];
// hart 0 configurations
28'hc002000: if (memwrite) intEn[31:1] <= HWDATA[31:1];
28'hc002004: if (memwrite) intEn[53:32] <= HWDATA[22:0];
endcase
end
end else begin // 32-bit
always @(posedge HCLK) begin
// reading
case(entry)
// priority assignments
28'hc000004: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[1]};
28'hc000008: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[2]};
28'hc00000c: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[3]};
28'hc000010: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[4]};
28'hc000014: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[5]};
28'hc000018: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[6]};
28'hc00001c: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[7]};
28'hc000020: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[8]};
28'hc000024: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[9]};
28'hc000028: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[10]};
28'hc00002c: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[11]};
28'hc000030: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[12]};
28'hc000034: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[13]};
28'hc000038: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[14]};
28'hc00003c: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[15]};
28'hc000040: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[16]};
28'hc000044: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[17]};
28'hc000048: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[18]};
28'hc00004c: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[19]};
28'hc000050: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[20]};
28'hc000054: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[21]};
28'hc000058: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[22]};
28'hc00005c: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[23]};
28'hc000060: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[24]};
28'hc000064: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[25]};
28'hc000068: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[26]};
28'hc00006c: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[27]};
28'hc000070: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[28]};
28'hc000074: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[29]};
28'hc000078: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[30]};
28'hc00007c: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[31]};
28'hc000080: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[32]};
28'hc000084: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[33]};
28'hc000088: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[34]};
28'hc00008c: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[35]};
28'hc000090: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[36]};
28'hc000094: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[37]};
28'hc000098: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[38]};
28'hc00009c: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[39]};
28'hc0000a0: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[40]};
28'hc0000a4: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[41]};
28'hc0000a8: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[42]};
28'hc0000ac: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[43]};
28'hc0000b0: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[44]};
28'hc0000b4: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[45]};
28'hc0000b8: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[46]};
28'hc0000bc: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[47]};
28'hc0000c0: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[48]};
28'hc0000c4: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[49]};
28'hc0000c8: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[50]};
28'hc0000cc: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[51]};
28'hc0000d0: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[52]};
28'hc0000d4: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[53]};
// hart 0 configurations
28'hc001000: HREADPLIC <= {{(`XLEN-32){1'b0}},intPending[31:1],1'b0};
28'hc001004: HREADPLIC <= {{(`XLEN-22){1'b0}},intPending[53:32]};
28'hc002000: HREADPLIC <= {{(`XLEN-32){1'b0}},intEn[31:1],1'b0};
28'hc002004: HREADPLIC <= {{(`XLEN-22){1'b0}},intEn[53:32]};
28'hc200000: HREADPLIC <= {{(`XLEN-3){1'b0}},intThreshold[2:0]};
28'hc200004: HREADPLIC <= {{(`XLEN-32){1'b0}},intClaim[31:0]};
default: HREADPLIC <= 0;
endcase
// writing
case(entry)
// priority assignments
28'hc000004: if (memwrite) intPriority[1] <= HWDATA[2:0];
28'hc000008: if (memwrite) intPriority[2] <= HWDATA[2:0];
28'hc00000c: if (memwrite) intPriority[3] <= HWDATA[2:0];
28'hc000010: if (memwrite) intPriority[4] <= HWDATA[2:0];
28'hc000014: if (memwrite) intPriority[5] <= HWDATA[2:0];
28'hc000018: if (memwrite) intPriority[6] <= HWDATA[2:0];
28'hc00001c: if (memwrite) intPriority[7] <= HWDATA[2:0];
28'hc000020: if (memwrite) intPriority[8] <= HWDATA[2:0];
28'hc000024: if (memwrite) intPriority[9] <= HWDATA[2:0];
28'hc000028: if (memwrite) intPriority[10] <= HWDATA[2:0];
28'hc00002c: if (memwrite) intPriority[11] <= HWDATA[2:0];
28'hc000030: if (memwrite) intPriority[12] <= HWDATA[2:0];
28'hc000034: if (memwrite) intPriority[13] <= HWDATA[2:0];
28'hc000038: if (memwrite) intPriority[14] <= HWDATA[2:0];
28'hc00003c: if (memwrite) intPriority[15] <= HWDATA[2:0];
28'hc000040: if (memwrite) intPriority[16] <= HWDATA[2:0];
28'hc000044: if (memwrite) intPriority[17] <= HWDATA[2:0];
28'hc000048: if (memwrite) intPriority[18] <= HWDATA[2:0];
28'hc00004c: if (memwrite) intPriority[19] <= HWDATA[2:0];
28'hc000050: if (memwrite) intPriority[20] <= HWDATA[2:0];
28'hc000054: if (memwrite) intPriority[21] <= HWDATA[2:0];
28'hc000058: if (memwrite) intPriority[22] <= HWDATA[2:0];
28'hc00005c: if (memwrite) intPriority[23] <= HWDATA[2:0];
28'hc000060: if (memwrite) intPriority[24] <= HWDATA[2:0];
28'hc000064: if (memwrite) intPriority[25] <= HWDATA[2:0];
28'hc000068: if (memwrite) intPriority[26] <= HWDATA[2:0];
28'hc00006c: if (memwrite) intPriority[27] <= HWDATA[2:0];
28'hc000070: if (memwrite) intPriority[28] <= HWDATA[2:0];
28'hc000074: if (memwrite) intPriority[29] <= HWDATA[2:0];
28'hc000078: if (memwrite) intPriority[30] <= HWDATA[2:0];
28'hc00007c: if (memwrite) intPriority[31] <= HWDATA[2:0];
28'hc000080: if (memwrite) intPriority[32] <= HWDATA[2:0];
28'hc000084: if (memwrite) intPriority[33] <= HWDATA[2:0];
28'hc000088: if (memwrite) intPriority[34] <= HWDATA[2:0];
28'hc00008c: if (memwrite) intPriority[35] <= HWDATA[2:0];
28'hc000090: if (memwrite) intPriority[36] <= HWDATA[2:0];
28'hc000094: if (memwrite) intPriority[37] <= HWDATA[2:0];
28'hc000098: if (memwrite) intPriority[38] <= HWDATA[2:0];
28'hc00009c: if (memwrite) intPriority[39] <= HWDATA[2:0];
28'hc0000a0: if (memwrite) intPriority[40] <= HWDATA[2:0];
28'hc0000a4: if (memwrite) intPriority[41] <= HWDATA[2:0];
28'hc0000a8: if (memwrite) intPriority[42] <= HWDATA[2:0];
28'hc0000ac: if (memwrite) intPriority[43] <= HWDATA[2:0];
28'hc0000b0: if (memwrite) intPriority[44] <= HWDATA[2:0];
28'hc0000b4: if (memwrite) intPriority[45] <= HWDATA[2:0];
28'hc0000b8: if (memwrite) intPriority[46] <= HWDATA[2:0];
28'hc0000bc: if (memwrite) intPriority[47] <= HWDATA[2:0];
28'hc0000c0: if (memwrite) intPriority[48] <= HWDATA[2:0];
28'hc0000c4: if (memwrite) intPriority[49] <= HWDATA[2:0];
28'hc0000c8: if (memwrite) intPriority[50] <= HWDATA[2:0];
28'hc0000cc: if (memwrite) intPriority[51] <= HWDATA[2:0];
28'hc0000d0: if (memwrite) intPriority[52] <= HWDATA[2:0];
28'hc0000d4: if (memwrite) intPriority[53] <= HWDATA[2:0];
// hart 0 configurations
28'hc002000: if (memwrite) intEn[31:1] <= HWDATA[31:1];
28'hc002004: if (memwrite) intEn[53:32] <= HWDATA[22:0];
endcase
end
end
endgenerate
endmodule

2
wally-pipelined/src/uncore/uartPC16550D.sv
View File

@ -49,7 +49,7 @@ module uartPC16550D(
output logic SOUT, RTSb, DTRb, OUT1b, OUT2b output logic SOUT, RTSb, DTRb, OUT1b, OUT2b
); );
// transmit and receive states // transmit and receive states // *** neeed to work on synth warning -- it wants to make enums 32 bits by default
typedef enum {UART_IDLE, UART_ACTIVE, UART_DONE, UART_BREAK} statetype; typedef enum {UART_IDLE, UART_ACTIVE, UART_DONE, UART_BREAK} statetype;
// Registers // Registers

2
wally-pipelined/src/uncore/uncore.sv
View File

@ -67,7 +67,7 @@ module uncore (
logic [`XLEN-1:0] HREADBootTim; logic [`XLEN-1:0] HREADBootTim;
logic HSELBootTim, HSELBootTimD, HRESPBootTim, HREADYBootTim; logic HSELBootTim, HSELBootTimD, HRESPBootTim, HREADYBootTim;
logic [1:0] MemRWboottim; logic [1:0] MemRWboottim;
logic UARTIntr;// *** will need to tie INTR to an interrupt handler logic UARTIntr,GPIOIntr;
// AHB Address decoder // AHB Address decoder

2
wally-pipelined/testbench/testbench-imperas.sv
View File

@ -356,7 +356,7 @@ module testbench();
}; };
string tests32periph[] = '{ string tests32periph[] = '{
"rv32i-periph/WALLY-PLIC", "2000" "rv32i-periph/WALLY-PLIC", "2080"
}; };