mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Moved generate of conditional units to hart
This commit is contained in:
David Harris
commit
193885c958
@ -49,7 +49,7 @@ connect_debug_port u_ila_0/probe7 [get_nets [list {wallypipelinedsoc/hart/PCM[0]
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create_debug_port u_ila_0 probe
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create_debug_port u_ila_0 probe
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set_property port_width 64 [get_debug_ports u_ila_0/probe8]
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set_property port_width 64 [get_debug_ports u_ila_0/probe8]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
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connect_debug_port u_ila_0/probe8 [get_nets [list {wallypipelinedsoc/hart/MemAdrM[0]} {wallypipelinedsoc/hart/MemAdrM[1]} {wallypipelinedsoc/hart/MemAdrM[2]} {wallypipelinedsoc/hart/MemAdrM[3]} {wallypipelinedsoc/hart/MemAdrM[4]} {wallypipelinedsoc/hart/MemAdrM[5]} {wallypipelinedsoc/hart/MemAdrM[6]} {wallypipelinedsoc/hart/MemAdrM[7]} {wallypipelinedsoc/hart/MemAdrM[8]} {wallypipelinedsoc/hart/MemAdrM[9]} {wallypipelinedsoc/hart/MemAdrM[10]} {wallypipelinedsoc/hart/MemAdrM[11]} {wallypipelinedsoc/hart/MemAdrM[12]} {wallypipelinedsoc/hart/MemAdrM[13]} {wallypipelinedsoc/hart/MemAdrM[14]} {wallypipelinedsoc/hart/MemAdrM[15]} {wallypipelinedsoc/hart/MemAdrM[16]} {wallypipelinedsoc/hart/MemAdrM[17]} {wallypipelinedsoc/hart/MemAdrM[18]} {wallypipelinedsoc/hart/MemAdrM[19]} {wallypipelinedsoc/hart/MemAdrM[20]} {wallypipelinedsoc/hart/MemAdrM[21]} {wallypipelinedsoc/hart/MemAdrM[22]} {wallypipelinedsoc/hart/MemAdrM[23]} {wallypipelinedsoc/hart/MemAdrM[24]} {wallypipelinedsoc/hart/MemAdrM[25]} {wallypipelinedsoc/hart/MemAdrM[26]} {wallypipelinedsoc/hart/MemAdrM[27]} {wallypipelinedsoc/hart/MemAdrM[28]} {wallypipelinedsoc/hart/MemAdrM[29]} {wallypipelinedsoc/hart/MemAdrM[30]} {wallypipelinedsoc/hart/MemAdrM[31]} {wallypipelinedsoc/hart/MemAdrM[32]} {wallypipelinedsoc/hart/MemAdrM[33]} {wallypipelinedsoc/hart/MemAdrM[34]} {wallypipelinedsoc/hart/MemAdrM[35]} {wallypipelinedsoc/hart/MemAdrM[36]} {wallypipelinedsoc/hart/MemAdrM[37]} {wallypipelinedsoc/hart/MemAdrM[38]} {wallypipelinedsoc/hart/MemAdrM[39]} {wallypipelinedsoc/hart/MemAdrM[40]} {wallypipelinedsoc/hart/MemAdrM[41]} {wallypipelinedsoc/hart/MemAdrM[42]} {wallypipelinedsoc/hart/MemAdrM[43]} {wallypipelinedsoc/hart/MemAdrM[44]} {wallypipelinedsoc/hart/MemAdrM[45]} {wallypipelinedsoc/hart/MemAdrM[46]} {wallypipelinedsoc/hart/MemAdrM[47]} {wallypipelinedsoc/hart/MemAdrM[48]} {wallypipelinedsoc/hart/MemAdrM[49]} {wallypipelinedsoc/hart/MemAdrM[50]} {wallypipelinedsoc/hart/MemAdrM[51]} {wallypipelinedsoc/hart/MemAdrM[52]} {wallypipelinedsoc/hart/MemAdrM[53]} {wallypipelinedsoc/hart/MemAdrM[54]} {wallypipelinedsoc/hart/MemAdrM[55]} {wallypipelinedsoc/hart/MemAdrM[56]} {wallypipelinedsoc/hart/MemAdrM[57]} {wallypipelinedsoc/hart/MemAdrM[58]} {wallypipelinedsoc/hart/MemAdrM[59]} {wallypipelinedsoc/hart/MemAdrM[60]} {wallypipelinedsoc/hart/MemAdrM[61]} {wallypipelinedsoc/hart/MemAdrM[62]} {wallypipelinedsoc/hart/MemAdrM[63]} ]]
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connect_debug_port u_ila_0/probe8 [get_nets [list {wallypipelinedsoc/hart/IEUAdrM[0]} {wallypipelinedsoc/hart/IEUAdrM[1]} {wallypipelinedsoc/hart/IEUAdrM[2]} {wallypipelinedsoc/hart/IEUAdrM[3]} {wallypipelinedsoc/hart/IEUAdrM[4]} {wallypipelinedsoc/hart/IEUAdrM[5]} {wallypipelinedsoc/hart/IEUAdrM[6]} {wallypipelinedsoc/hart/IEUAdrM[7]} {wallypipelinedsoc/hart/IEUAdrM[8]} {wallypipelinedsoc/hart/IEUAdrM[9]} {wallypipelinedsoc/hart/IEUAdrM[10]} {wallypipelinedsoc/hart/IEUAdrM[11]} {wallypipelinedsoc/hart/IEUAdrM[12]} {wallypipelinedsoc/hart/IEUAdrM[13]} {wallypipelinedsoc/hart/IEUAdrM[14]} {wallypipelinedsoc/hart/IEUAdrM[15]} {wallypipelinedsoc/hart/IEUAdrM[16]} {wallypipelinedsoc/hart/IEUAdrM[17]} {wallypipelinedsoc/hart/IEUAdrM[18]} {wallypipelinedsoc/hart/IEUAdrM[19]} {wallypipelinedsoc/hart/IEUAdrM[20]} {wallypipelinedsoc/hart/IEUAdrM[21]} {wallypipelinedsoc/hart/IEUAdrM[22]} {wallypipelinedsoc/hart/IEUAdrM[23]} {wallypipelinedsoc/hart/IEUAdrM[24]} {wallypipelinedsoc/hart/IEUAdrM[25]} {wallypipelinedsoc/hart/IEUAdrM[26]} {wallypipelinedsoc/hart/IEUAdrM[27]} {wallypipelinedsoc/hart/IEUAdrM[28]} {wallypipelinedsoc/hart/IEUAdrM[29]} {wallypipelinedsoc/hart/IEUAdrM[30]} {wallypipelinedsoc/hart/IEUAdrM[31]} {wallypipelinedsoc/hart/IEUAdrM[32]} {wallypipelinedsoc/hart/IEUAdrM[33]} {wallypipelinedsoc/hart/IEUAdrM[34]} {wallypipelinedsoc/hart/IEUAdrM[35]} {wallypipelinedsoc/hart/IEUAdrM[36]} {wallypipelinedsoc/hart/IEUAdrM[37]} {wallypipelinedsoc/hart/IEUAdrM[38]} {wallypipelinedsoc/hart/IEUAdrM[39]} {wallypipelinedsoc/hart/IEUAdrM[40]} {wallypipelinedsoc/hart/IEUAdrM[41]} {wallypipelinedsoc/hart/IEUAdrM[42]} {wallypipelinedsoc/hart/IEUAdrM[43]} {wallypipelinedsoc/hart/IEUAdrM[44]} {wallypipelinedsoc/hart/IEUAdrM[45]} {wallypipelinedsoc/hart/IEUAdrM[46]} {wallypipelinedsoc/hart/IEUAdrM[47]} {wallypipelinedsoc/hart/IEUAdrM[48]} {wallypipelinedsoc/hart/IEUAdrM[49]} {wallypipelinedsoc/hart/IEUAdrM[50]} {wallypipelinedsoc/hart/IEUAdrM[51]} {wallypipelinedsoc/hart/IEUAdrM[52]} {wallypipelinedsoc/hart/IEUAdrM[53]} {wallypipelinedsoc/hart/IEUAdrM[54]} {wallypipelinedsoc/hart/IEUAdrM[55]} {wallypipelinedsoc/hart/IEUAdrM[56]} {wallypipelinedsoc/hart/IEUAdrM[57]} {wallypipelinedsoc/hart/IEUAdrM[58]} {wallypipelinedsoc/hart/IEUAdrM[59]} {wallypipelinedsoc/hart/IEUAdrM[60]} {wallypipelinedsoc/hart/IEUAdrM[61]} {wallypipelinedsoc/hart/IEUAdrM[62]} {wallypipelinedsoc/hart/IEUAdrM[63]} ]]
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create_debug_port u_ila_0 probe
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create_debug_port u_ila_0 probe
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set_property port_width 32 [get_debug_ports u_ila_0/probe9]
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set_property port_width 32 [get_debug_ports u_ila_0/probe9]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
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@ -75,7 +75,7 @@ add wave -noupdate -expand -group {Memory Stage} /testbench/ExpectedPCM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM
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add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
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add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
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add wave -noupdate -expand -group {Memory Stage} /testbench/textM
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add wave -noupdate -expand -group {Memory Stage} /testbench/textM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/MemAdrM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/IEUAdrM
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add wave -noupdate -expand -group {WriteBack stage} /testbench/checkInstrW
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add wave -noupdate -expand -group {WriteBack stage} /testbench/checkInstrW
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add wave -noupdate -expand -group {WriteBack stage} /testbench/InstrValidW
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add wave -noupdate -expand -group {WriteBack stage} /testbench/InstrValidW
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add wave -noupdate -expand -group {WriteBack stage} /testbench/PCW
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add wave -noupdate -expand -group {WriteBack stage} /testbench/PCW
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@ -5,52 +5,51 @@ add wave -noupdate /testbench/reset
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add wave -noupdate /testbench/test
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add wave -noupdate /testbench/test
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add wave -noupdate /testbench/memfilename
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add wave -noupdate /testbench/memfilename
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add wave -noupdate /testbench/dut/hart/SATP_REGW
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add wave -noupdate /testbench/dut/hart/SATP_REGW
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add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName
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add wave -noupdate -group {Execution Stage} /testbench/dut/hart/ifu/PCE
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
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add wave -noupdate -group {Execution Stage} /testbench/InstrEName
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add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
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add wave -noupdate -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrValidM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrValidM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/PCM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/PCM
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add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
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add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/MemAdrM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/IEUAdrM
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add wave -noupdate /testbench/dut/hart/ieu/dp/ResultM
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add wave -noupdate /testbench/dut/hart/ieu/dp/ResultM
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add wave -noupdate /testbench/dut/hart/ieu/dp/ResultW
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add wave -noupdate /testbench/dut/hart/ieu/dp/ResultW
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM
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add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM
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add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM
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add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/RetM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/TrapM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/StoreStallD
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/StoreStallD
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/ICacheStallF
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/LSUStall
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LSUStall
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/MulDivStallD
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
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add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
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add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
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add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM
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add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW
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add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
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add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR
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add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR
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add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
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add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
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add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
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add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
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@ -98,12 +97,12 @@ add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/if
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredClassNonCFIWrongE
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredClassNonCFIWrongE
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE
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add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE
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add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE
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add wave -noupdate -expand -group {instruction pipeline} /testbench/InstrFName
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add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
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add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/icache/FinalInstrRawF
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add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/icache/FinalInstrRawF
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add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD
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add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD
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add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE
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add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE
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add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM
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add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM
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add wave -noupdate -expand -group {instruction pipeline} /testbench/InstrW
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add wave -noupdate -group {instruction pipeline} /testbench/InstrW
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNextF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNextF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCPlus2or4F
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCPlus2or4F
|
||||||
@ -127,7 +126,6 @@ add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rd1
|
|||||||
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rd2
|
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rd2
|
||||||
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/we3
|
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/we3
|
||||||
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/wd3
|
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/wd3
|
||||||
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/IntResultW
|
|
||||||
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ReadDataW
|
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ReadDataW
|
||||||
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
|
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
|
||||||
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
|
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
|
||||||
@ -135,8 +133,6 @@ add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart
|
|||||||
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/A
|
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/A
|
||||||
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/B
|
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/B
|
||||||
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ALUControl
|
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ALUControl
|
||||||
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/result
|
|
||||||
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/FlagsE
|
|
||||||
add wave -noupdate -group alu -divider internals
|
add wave -noupdate -group alu -divider internals
|
||||||
add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D
|
add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D
|
||||||
add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D
|
add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D
|
||||||
@ -155,13 +151,12 @@ add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/Write
|
|||||||
add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/ALUResultE
|
add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/ALUResultE
|
||||||
add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcAE
|
add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcAE
|
||||||
add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE
|
add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE
|
||||||
add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCNextF
|
add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCNextF
|
||||||
add wave -noupdate -expand -group PCS /testbench/dut/hart/PCF
|
add wave -noupdate -group PCS /testbench/dut/hart/PCF
|
||||||
add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCD
|
add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCD
|
||||||
add wave -noupdate -expand -group PCS /testbench/dut/hart/PCE
|
add wave -noupdate -group PCS /testbench/dut/hart/PCE
|
||||||
add wave -noupdate -expand -group PCS /testbench/dut/hart/PCM
|
add wave -noupdate -group PCS /testbench/dut/hart/PCM
|
||||||
add wave -noupdate -expand -group PCS /testbench/PCW
|
add wave -noupdate -group PCS /testbench/PCW
|
||||||
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/InstrD
|
|
||||||
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/ForwardedSrcAE
|
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/ForwardedSrcAE
|
||||||
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/ForwardedSrcBE
|
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/ForwardedSrcBE
|
||||||
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/Funct3E
|
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/Funct3E
|
||||||
@ -173,83 +168,78 @@ add wave -noupdate -group muldiv /testbench/dut/hart/mdu/FlushM
|
|||||||
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/FlushW
|
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/FlushW
|
||||||
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/MulDivResultW
|
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/MulDivResultW
|
||||||
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/DivBusyE
|
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/DivBusyE
|
||||||
add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/fsm1/CURRENT_STATE
|
|
||||||
add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/N
|
|
||||||
add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/D
|
|
||||||
add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/Q
|
|
||||||
add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/rem0
|
|
||||||
add wave -noupdate -group icache -color Gold /testbench/dut/hart/ifu/icache/controller/CurrState
|
add wave -noupdate -group icache -color Gold /testbench/dut/hart/ifu/icache/controller/CurrState
|
||||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/BasePAdrF
|
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/BasePAdrF
|
||||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/WayHit
|
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/WayHit
|
||||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/genblk1/cachereplacementpolicy/BlockReplacementBits
|
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/genblk1/cachereplacementpolicy/BlockReplacementBits
|
||||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/genblk1/cachereplacementpolicy/EncVicWay
|
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/genblk1/cachereplacementpolicy/EncVicWay
|
||||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/VictimWay
|
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/VictimWay
|
||||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/ifu/icache/MemWay[0]/WriteEnable}
|
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/ifu/icache/MemWay[0]/WriteEnable}
|
||||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/ifu/icache/MemWay[0]/SetValid}
|
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/ifu/icache/MemWay[0]/SetValid}
|
||||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[0]/CacheTagMem/StoredData}
|
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[0]/CacheTagMem/StoredData}
|
||||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/ifu/icache/MemWay[0]/ValidBits}
|
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/ifu/icache/MemWay[0]/ValidBits}
|
||||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[0]/CacheDataMem/StoredData}
|
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[0]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[1]/CacheDataMem/StoredData}
|
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[1]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[2]/CacheDataMem/StoredData}
|
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[2]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[3]/CacheDataMem/StoredData}
|
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[3]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/ifu/icache/MemWay[1]/WriteEnable}
|
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/ifu/icache/MemWay[1]/WriteEnable}
|
||||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/ifu/icache/MemWay[1]/WriteWordEnable}
|
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/ifu/icache/MemWay[1]/WriteWordEnable}
|
||||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[1]/CacheTagMem/StoredData}
|
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[1]/CacheTagMem/StoredData}
|
||||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/ifu/icache/MemWay[1]/ValidBits}
|
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/ifu/icache/MemWay[1]/ValidBits}
|
||||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[0]/CacheDataMem/StoredData}
|
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[0]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[1]/CacheDataMem/StoredData}
|
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[1]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[2]/CacheDataMem/StoredData}
|
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[2]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[3]/CacheDataMem/StoredData}
|
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[3]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/ifu/icache/MemWay[2]/WriteEnable}
|
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/ifu/icache/MemWay[2]/WriteEnable}
|
||||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/ifu/icache/MemWay[2]/SetValid}
|
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/ifu/icache/MemWay[2]/SetValid}
|
||||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[2]/CacheTagMem/StoredData}
|
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[2]/CacheTagMem/StoredData}
|
||||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/ifu/icache/MemWay[2]/ValidBits}
|
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/ifu/icache/MemWay[2]/ValidBits}
|
||||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[0]/CacheDataMem/StoredData}
|
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[0]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[1]/CacheDataMem/StoredData}
|
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[1]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[2]/CacheDataMem/StoredData}
|
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[2]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[3]/CacheDataMem/StoredData}
|
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[3]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/WriteEnable}
|
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/WriteEnable}
|
||||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/SetValid}
|
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/SetValid}
|
||||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[3]/CacheTagMem/StoredData}
|
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[3]/CacheTagMem/StoredData}
|
||||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/DirtyBits}
|
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/DirtyBits}
|
||||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/ValidBits}
|
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/ValidBits}
|
||||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[0]/CacheDataMem/StoredData}
|
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[0]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[1]/CacheDataMem/StoredData}
|
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[1]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[2]/CacheDataMem/StoredData}
|
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[2]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -group icache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[3]/CacheDataMem/StoredData}
|
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[3]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/controller/NextState
|
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/controller/NextState
|
||||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/ITLBMissF
|
add wave -noupdate -group icache /testbench/dut/hart/ifu/ITLBMissF
|
||||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ITLBWriteF
|
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ITLBWriteF
|
||||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ReadLineF
|
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ReadLineF
|
||||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/PCNextIndexF
|
|
||||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ReadLineF
|
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ReadLineF
|
||||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/BasePAdrF
|
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/BasePAdrF
|
||||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit
|
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit
|
||||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill
|
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill
|
||||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF
|
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF
|
||||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/SavePC
|
|
||||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
|
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
|
||||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/UnalignedSelect
|
|
||||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
|
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
|
||||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntReset
|
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntReset
|
||||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn
|
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn
|
||||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntEn
|
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntEn
|
||||||
|
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/SelAdr
|
||||||
|
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/RAdr
|
||||||
|
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/FinalInstrRawF
|
||||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/InstrPAdrF
|
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/InstrPAdrF
|
||||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/InstrInF
|
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/InstrInF
|
||||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag
|
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag
|
||||||
@ -279,10 +269,9 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/HMASTLOCK
|
|||||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD
|
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD
|
||||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED
|
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED
|
||||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED
|
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED
|
||||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/StallW
|
add wave -noupdate -expand -group lsu /testbench/dut/hart/hzu/LSUStall
|
||||||
add wave -noupdate -expand -group lsu -expand -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/SelPTW
|
add wave -noupdate -expand -group lsu -expand -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/SelPTW
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcachefsm/CurrState
|
add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcachefsm/CurrState
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WalkerPageFaultM
|
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM
|
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM
|
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM
|
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM
|
||||||
@ -351,10 +340,10 @@ add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM w
|
|||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearValid
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearValid
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/SetDirty
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/SetDirty
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearDirty
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearDirty
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WayHit}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WayHit}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Valid}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Valid}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Dirty}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Dirty}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ReadTag}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ReadTag}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WayHit}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WayHit}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Valid}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Valid}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Dirty}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Dirty}
|
||||||
@ -375,17 +364,16 @@ add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testb
|
|||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay
|
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay
|
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty
|
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/FlushDCacheM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/FlushDCacheM
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataM
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall
|
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/FlushAdrFlag
|
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/FlushAdrFlag
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit
|
add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit
|
add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit
|
||||||
@ -421,19 +409,19 @@ add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PM
|
|||||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPInstrAccessFaultF
|
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPInstrAccessFaultF
|
||||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM
|
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM
|
||||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM
|
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker -color Gold /testbench/dut/hart/lsu/hptw/genblk1/WalkerState
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/hart/lsu/hptw/genblk1/WalkerState
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/PCF
|
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/PCF
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/genblk1/TranslationVAdr
|
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/genblk1/TranslationVAdr
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/TranslationPAdr
|
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/TranslationPAdr
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/HPTWReadPTE
|
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/HPTWReadPTE
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/PTE
|
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/PTE
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/ITLBMissF
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/ITLBMissF
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/DTLBMissM
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/DTLBMissM
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/ITLBWriteF
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/ITLBWriteF
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/DTLBWriteM
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/DTLBWriteM
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerInstrPageFaultF
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerInstrPageFaultF
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerLoadPageFaultM
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerLoadPageFaultM
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerStorePageFaultM
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerStorePageFaultM
|
||||||
add wave -noupdate -group csr /testbench/dut/hart/priv/csr/MIP_REGW
|
add wave -noupdate -group csr /testbench/dut/hart/priv/csr/MIP_REGW
|
||||||
add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/TLBWrite
|
add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/TLBWrite
|
||||||
add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF
|
add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF
|
||||||
@ -508,28 +496,18 @@ add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HSELUART
|
|||||||
add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HADDR
|
add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HADDR
|
||||||
add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWRITE
|
add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWRITE
|
||||||
add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWDATA
|
add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWDATA
|
||||||
add wave -noupdate -color Gold /testbench/dut/hart/lsu/dcache/subwordread/offset0
|
add wave -noupdate /testbench/dut/hart/lsu/CurrState
|
||||||
add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/offset1
|
add wave -noupdate /testbench/dut/hart/lsu/InterlockStall
|
||||||
add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/offset2
|
add wave -noupdate /testbench/dut/hart/ifu/icache/PCNextF
|
||||||
add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/offset3
|
|
||||||
add wave -noupdate /testbench/dut/hart/ExceptionM
|
|
||||||
add wave -noupdate /testbench/dut/hart/PendingInterruptM
|
|
||||||
add wave -noupdate /testbench/dut/hart/TrapM
|
|
||||||
add wave -noupdate /testbench/dut/hart/ifu/icache/CompressedF
|
|
||||||
add wave -noupdate /testbench/dut/hart/ifu/icache/PCPF
|
add wave -noupdate /testbench/dut/hart/ifu/icache/PCPF
|
||||||
add wave -noupdate /testbench/dut/hart/ifu/PCPFmmu
|
add wave -noupdate /testbench/dut/hart/lsu/WalkerInstrPageFaultF
|
||||||
add wave -noupdate /testbench/dut/hart/ifu/PCPF
|
add wave -noupdate /testbench/dut/hart/lsu/WalkerPageFaultM
|
||||||
add wave -noupdate /testbench/dut/hart/ifu/PCF
|
add wave -noupdate /testbench/dut/hart/lsu/dcache/RAdr
|
||||||
add wave -noupdate /testbench/dut/hart/ifu/immu/Translate
|
add wave -noupdate /testbench/dut/hart/lsu/dcache/SelAdrM
|
||||||
add wave -noupdate /testbench/dut/hart/ifu/icache/FinalInstrRawF
|
add wave -noupdate /testbench/dut/hart/lsu/SelReplayCPURequest
|
||||||
add wave -noupdate /testbench/dut/hart/ifu/icache/StallF
|
|
||||||
add wave -noupdate /testbench/dut/hart/ifu/icache/ICacheMemReadData
|
|
||||||
add wave -noupdate /testbench/dut/hart/ifu/icache/PCTagF
|
|
||||||
add wave -noupdate /testbench/dut/hart/ifu/icache/PCPSpillF
|
|
||||||
add wave -noupdate /testbench/dut/hart/ifu/icache/ICacheReadEn
|
|
||||||
TreeUpdate [SetDefaultTree]
|
TreeUpdate [SetDefaultTree]
|
||||||
WaveRestoreCursors {{Cursor 6} {122378 ns} 0}
|
WaveRestoreCursors {{Cursor 6} {24475 ns} 1} {{Cursor 2} {22501 ns} 1} {{Cursor 3} {3615 ns} 0}
|
||||||
quietly wave cursor active 1
|
quietly wave cursor active 3
|
||||||
configure wave -namecolwidth 250
|
configure wave -namecolwidth 250
|
||||||
configure wave -valuecolwidth 297
|
configure wave -valuecolwidth 297
|
||||||
configure wave -justifyvalue left
|
configure wave -justifyvalue left
|
||||||
@ -544,4 +522,4 @@ configure wave -griddelta 40
|
|||||||
configure wave -timeline 0
|
configure wave -timeline 0
|
||||||
configure wave -timelineunits ns
|
configure wave -timelineunits ns
|
||||||
update
|
update
|
||||||
WaveRestoreZoom {122227 ns} {122479 ns}
|
WaveRestoreZoom {3453 ns} {3729 ns}
|
||||||
|
|||||||
23
wally-pipelined/src/cache/dcache.sv
vendored
23
wally-pipelined/src/cache/dcache.sv
vendored
@ -36,7 +36,7 @@ module dcache
|
|||||||
input logic [6:0] Funct7M,
|
input logic [6:0] Funct7M,
|
||||||
input logic [1:0] AtomicM,
|
input logic [1:0] AtomicM,
|
||||||
input logic FlushDCacheM,
|
input logic FlushDCacheM,
|
||||||
input logic [11:0] IEUAdrE, // virtual address, but we only use the lower 12 bits.
|
input logic [11:0] MemAdrE, // virtual address, but we only use the lower 12 bits.
|
||||||
input logic [`PA_BITS-1:0] MemPAdrM, // physical address
|
input logic [`PA_BITS-1:0] MemPAdrM, // physical address
|
||||||
input logic [11:0] VAdr, // when hptw writes dtlb we use this address to index SRAM.
|
input logic [11:0] VAdr, // when hptw writes dtlb we use this address to index SRAM.
|
||||||
|
|
||||||
@ -50,15 +50,9 @@ module dcache
|
|||||||
// inputs from TLB and PMA/P
|
// inputs from TLB and PMA/P
|
||||||
input logic ExceptionM,
|
input logic ExceptionM,
|
||||||
input logic PendingInterruptM,
|
input logic PendingInterruptM,
|
||||||
input logic DTLBMissM,
|
|
||||||
input logic ITLBMissF,
|
|
||||||
input logic CacheableM,
|
input logic CacheableM,
|
||||||
input logic DTLBWriteM,
|
|
||||||
input logic ITLBWriteF,
|
|
||||||
input logic WalkerInstrPageFaultF,
|
|
||||||
// from ptw
|
// from ptw
|
||||||
input logic SelPTW,
|
input logic IgnoreRequest,
|
||||||
input logic WalkerPageFaultM,
|
|
||||||
output logic MemAfterIWalkDone,
|
output logic MemAfterIWalkDone,
|
||||||
// ahb side
|
// ahb side
|
||||||
(* mark_debug = "true" *)output logic [`PA_BITS-1:0] AHBPAdr, // to ahb
|
(* mark_debug = "true" *)output logic [`PA_BITS-1:0] AHBPAdr, // to ahb
|
||||||
@ -147,9 +141,10 @@ module dcache
|
|||||||
// Read Path CPU (IEU) side
|
// Read Path CPU (IEU) side
|
||||||
|
|
||||||
mux4 #(INDEXLEN)
|
mux4 #(INDEXLEN)
|
||||||
AdrSelMux(.d0(IEUAdrE[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
|
AdrSelMux(.d0(MemAdrE[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
|
||||||
.d1(VAdr[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
|
.d1(VAdr[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), // *** REMOVE
|
||||||
.d2(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
|
.d2(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
|
||||||
|
//.d2(VAdr[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
|
||||||
.d3(FlushAdr),
|
.d3(FlushAdr),
|
||||||
.s(SelAdrM),
|
.s(SelAdrM),
|
||||||
.y(RAdr));
|
.y(RAdr));
|
||||||
@ -353,14 +348,8 @@ module dcache
|
|||||||
.ExceptionM,
|
.ExceptionM,
|
||||||
.PendingInterruptM,
|
.PendingInterruptM,
|
||||||
.StallWtoDCache,
|
.StallWtoDCache,
|
||||||
.DTLBMissM,
|
|
||||||
.ITLBMissF,
|
|
||||||
.CacheableM,
|
.CacheableM,
|
||||||
.DTLBWriteM,
|
.IgnoreRequest,
|
||||||
.ITLBWriteF,
|
|
||||||
.WalkerInstrPageFaultF,
|
|
||||||
.SelPTW,
|
|
||||||
.WalkerPageFaultM,
|
|
||||||
.AHBAck, // from ahb
|
.AHBAck, // from ahb
|
||||||
.CacheHit,
|
.CacheHit,
|
||||||
.FetchCountFlag,
|
.FetchCountFlag,
|
||||||
|
|||||||
436
wally-pipelined/src/cache/dcachefsm.sv
vendored
436
wally-pipelined/src/cache/dcachefsm.sv
vendored
@ -36,16 +36,9 @@ module dcachefsm
|
|||||||
input logic ExceptionM,
|
input logic ExceptionM,
|
||||||
input logic PendingInterruptM,
|
input logic PendingInterruptM,
|
||||||
input logic StallWtoDCache,
|
input logic StallWtoDCache,
|
||||||
// mmu inputs
|
|
||||||
input logic DTLBMissM,
|
|
||||||
input logic ITLBMissF,
|
|
||||||
input logic CacheableM,
|
input logic CacheableM,
|
||||||
input logic DTLBWriteM,
|
|
||||||
input logic ITLBWriteF,
|
|
||||||
input logic WalkerInstrPageFaultF,
|
|
||||||
// hptw inputs
|
// hptw inputs
|
||||||
input logic SelPTW,
|
input logic IgnoreRequest,
|
||||||
input logic WalkerPageFaultM,
|
|
||||||
// Bus inputs
|
// Bus inputs
|
||||||
input logic AHBAck, // from ahb
|
input logic AHBAck, // from ahb
|
||||||
// dcache internals
|
// dcache internals
|
||||||
@ -101,36 +94,11 @@ module dcachefsm
|
|||||||
STATE_MISS_READ_WORD_DELAY,
|
STATE_MISS_READ_WORD_DELAY,
|
||||||
STATE_MISS_WRITE_WORD,
|
STATE_MISS_WRITE_WORD,
|
||||||
|
|
||||||
STATE_PTW_READY,
|
|
||||||
STATE_PTW_READ_MISS_FETCH_WDV,
|
|
||||||
STATE_PTW_READ_MISS_FETCH_DONE,
|
|
||||||
STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK,
|
|
||||||
STATE_PTW_READ_MISS_EVICT_DIRTY,
|
|
||||||
STATE_PTW_READ_MISS_READ_WORD,
|
|
||||||
STATE_PTW_READ_MISS_READ_WORD_DELAY,
|
|
||||||
STATE_PTW_ACCESS_AFTER_WALK,
|
|
||||||
|
|
||||||
STATE_UNCACHED_WRITE,
|
STATE_UNCACHED_WRITE,
|
||||||
STATE_UNCACHED_WRITE_DONE,
|
STATE_UNCACHED_WRITE_DONE,
|
||||||
STATE_UNCACHED_READ,
|
STATE_UNCACHED_READ,
|
||||||
STATE_UNCACHED_READ_DONE,
|
STATE_UNCACHED_READ_DONE,
|
||||||
|
|
||||||
STATE_PTW_FAULT_READY,
|
|
||||||
STATE_PTW_FAULT_CPU_BUSY,
|
|
||||||
STATE_PTW_FAULT_MISS_FETCH_WDV,
|
|
||||||
STATE_PTW_FAULT_MISS_FETCH_DONE,
|
|
||||||
STATE_PTW_FAULT_MISS_WRITE_CACHE_BLOCK,
|
|
||||||
STATE_PTW_FAULT_MISS_READ_WORD,
|
|
||||||
STATE_PTW_FAULT_MISS_READ_WORD_DELAY,
|
|
||||||
STATE_PTW_FAULT_MISS_WRITE_WORD,
|
|
||||||
STATE_PTW_FAULT_MISS_WRITE_WORD_DELAY,
|
|
||||||
STATE_PTW_FAULT_MISS_EVICT_DIRTY,
|
|
||||||
|
|
||||||
STATE_PTW_FAULT_UNCACHED_WRITE,
|
|
||||||
STATE_PTW_FAULT_UNCACHED_WRITE_DONE,
|
|
||||||
STATE_PTW_FAULT_UNCACHED_READ,
|
|
||||||
STATE_PTW_FAULT_UNCACHED_READ_DONE,
|
|
||||||
|
|
||||||
STATE_CPU_BUSY,
|
STATE_CPU_BUSY,
|
||||||
STATE_CPU_BUSY_FINISH_AMO,
|
STATE_CPU_BUSY_FINISH_AMO,
|
||||||
|
|
||||||
@ -191,18 +159,16 @@ module dcachefsm
|
|||||||
LRUWriteEn = 1'b0;
|
LRUWriteEn = 1'b0;
|
||||||
CommittedM = 1'b0;
|
CommittedM = 1'b0;
|
||||||
|
|
||||||
|
|
||||||
// TLB Miss
|
// TLB Miss
|
||||||
if(((AnyCPUReqM & DTLBMissM) | ITLBMissF) & ~(ExceptionM | PendingInterruptM)) begin
|
if(IgnoreRequest) begin
|
||||||
// the LSU arbiter has not yet selected the PTW.
|
// the LSU arbiter has not yet selected the PTW.
|
||||||
// The CPU needs to be stalled until that happens.
|
// The CPU needs to be stalled until that happens.
|
||||||
// If we set DCacheStall for 1 cycle before going to
|
// If we set DCacheStall for 1 cycle before going to
|
||||||
// PTW ready the CPU will stall.
|
// PTW ready the CPU will stall.
|
||||||
// The page table walker asserts it's control 1 cycle
|
// The page table walker asserts it's control 1 cycle
|
||||||
// after the TLBs miss.
|
// after the TLBs miss.
|
||||||
CommittedM = 1'b1;
|
// CommittedM = 1'b1; ??? *** Not Sure yet.
|
||||||
DCacheStall = 1'b1;
|
NextState = STATE_READY;
|
||||||
NextState = STATE_PTW_READY;
|
|
||||||
end
|
end
|
||||||
|
|
||||||
// Flush dcache to next level of memory
|
// Flush dcache to next level of memory
|
||||||
@ -215,7 +181,7 @@ module dcachefsm
|
|||||||
end
|
end
|
||||||
|
|
||||||
// amo hit
|
// amo hit
|
||||||
else if(AtomicM[1] & (&MemRWM) & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin
|
else if(AtomicM[1] & (&MemRWM) & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit) begin
|
||||||
SelAdrM = 2'b10;
|
SelAdrM = 2'b10;
|
||||||
DCacheStall = 1'b0;
|
DCacheStall = 1'b0;
|
||||||
|
|
||||||
@ -231,7 +197,7 @@ module dcachefsm
|
|||||||
end
|
end
|
||||||
end
|
end
|
||||||
// read hit valid cached
|
// read hit valid cached
|
||||||
else if(MemRWM[1] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin
|
else if(MemRWM[1] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit) begin
|
||||||
DCacheStall = 1'b0;
|
DCacheStall = 1'b0;
|
||||||
LRUWriteEn = 1'b1;
|
LRUWriteEn = 1'b1;
|
||||||
|
|
||||||
@ -244,7 +210,7 @@ module dcachefsm
|
|||||||
end
|
end
|
||||||
end
|
end
|
||||||
// write hit valid cached
|
// write hit valid cached
|
||||||
else if (MemRWM[0] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin
|
else if (MemRWM[0] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit) begin
|
||||||
SelAdrM = 2'b10;
|
SelAdrM = 2'b10;
|
||||||
DCacheStall = 1'b0;
|
DCacheStall = 1'b0;
|
||||||
SRAMWordWriteEnableM = 1'b1;
|
SRAMWordWriteEnableM = 1'b1;
|
||||||
@ -260,27 +226,27 @@ module dcachefsm
|
|||||||
end
|
end
|
||||||
end
|
end
|
||||||
// read or write miss valid cached
|
// read or write miss valid cached
|
||||||
else if((|MemRWM) & CacheableM & ~(ExceptionM | PendingInterruptM) & ~CacheHit & ~DTLBMissM) begin
|
else if((|MemRWM) & CacheableM & ~(ExceptionM | PendingInterruptM) & ~CacheHit) begin
|
||||||
NextState = STATE_MISS_FETCH_WDV;
|
NextState = STATE_MISS_FETCH_WDV;
|
||||||
CntReset = 1'b1;
|
CntReset = 1'b1;
|
||||||
DCacheStall = 1'b1;
|
DCacheStall = 1'b1;
|
||||||
end
|
end
|
||||||
// uncached write
|
// uncached write
|
||||||
else if(MemRWM[0] & ~CacheableM & ~(ExceptionM | PendingInterruptM) & ~DTLBMissM) begin
|
else if(MemRWM[0] & ~CacheableM & ~(ExceptionM | PendingInterruptM)) begin
|
||||||
NextState = STATE_UNCACHED_WRITE;
|
NextState = STATE_UNCACHED_WRITE;
|
||||||
CntReset = 1'b1;
|
CntReset = 1'b1;
|
||||||
DCacheStall = 1'b1;
|
DCacheStall = 1'b1;
|
||||||
AHBWrite = 1'b1;
|
AHBWrite = 1'b1;
|
||||||
end
|
end
|
||||||
// uncached read
|
// uncached read
|
||||||
else if(MemRWM[1] & ~CacheableM & ~(ExceptionM | PendingInterruptM) & ~DTLBMissM) begin
|
else if(MemRWM[1] & ~CacheableM & ~(ExceptionM | PendingInterruptM)) begin
|
||||||
NextState = STATE_UNCACHED_READ;
|
NextState = STATE_UNCACHED_READ;
|
||||||
CntReset = 1'b1;
|
CntReset = 1'b1;
|
||||||
DCacheStall = 1'b1;
|
DCacheStall = 1'b1;
|
||||||
AHBRead = 1'b1;
|
AHBRead = 1'b1;
|
||||||
end
|
end
|
||||||
// fault
|
// fault
|
||||||
else if(AnyCPUReqM & (ExceptionM | PendingInterruptM) & ~DTLBMissM) begin
|
else if(AnyCPUReqM & (ExceptionM | PendingInterruptM)) begin
|
||||||
NextState = STATE_READY;
|
NextState = STATE_READY;
|
||||||
end
|
end
|
||||||
else NextState = STATE_READY;
|
else NextState = STATE_READY;
|
||||||
@ -394,144 +360,7 @@ module dcachefsm
|
|||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
STATE_PTW_READY: begin
|
|
||||||
// now all output connect to PTW instead of CPU.
|
|
||||||
CommittedM = 1'b1;
|
|
||||||
SelAdrM = 2'b00;
|
|
||||||
DCacheStall = 1'b0;
|
|
||||||
LRUWriteEn = 1'b0;
|
|
||||||
CntReset = 1'b0;
|
|
||||||
|
|
||||||
// In this branch we remove stall and go back to ready. There is no request for memory from the
|
|
||||||
// datapath or the walker had a fault.
|
|
||||||
// types 3b, 4a, 4b, and 7c.
|
|
||||||
if ((DTLBMissM & WalkerPageFaultM) | // 3b or 7c (can have either itlb miss or not)
|
|
||||||
(ITLBMissF & (WalkerInstrPageFaultF | ITLBWriteF) & ~AnyCPUReqM & ~DTLBMissM) | // 4a and 4b
|
|
||||||
(DTLBMissM & ITLBMissF & WalkerPageFaultM)) begin // 7c *** BUG redundant with first condiction.
|
|
||||||
NextState = STATE_READY;
|
|
||||||
DCacheStall = 1'b0;
|
|
||||||
end
|
|
||||||
// in this branch we go back to ready, but there is a memory operation from
|
|
||||||
// the datapath so we MUST stall and replay the operation.
|
|
||||||
// types 3a and 5a
|
|
||||||
else if ((DTLBMissM & DTLBWriteM) | // 3a
|
|
||||||
(ITLBMissF & ITLBWriteF & AnyCPUReqM)) begin // 5a
|
|
||||||
NextState = STATE_READY;
|
|
||||||
DCacheStall = 1'b1;
|
|
||||||
SelAdrM = 2'b01;
|
|
||||||
end
|
|
||||||
|
|
||||||
// like 5a we want to stall and go to the ready state, but we also have to save
|
|
||||||
// the WalkerInstrPageFaultF so it is held until the end of the memory operation
|
|
||||||
// from the datapath.
|
|
||||||
// types 5b
|
|
||||||
else if (ITLBMissF & WalkerInstrPageFaultF & AnyCPUReqM) begin // 5b
|
|
||||||
NextState = STATE_PTW_FAULT_READY;
|
|
||||||
DCacheStall = 1'b1;
|
|
||||||
SelAdrM = 2'b01;
|
|
||||||
end
|
|
||||||
|
|
||||||
// in this branch we stay in ptw_ready because we are doing an itlb walk
|
|
||||||
// after a dtlb walk.
|
|
||||||
// types 7a and 7b.
|
|
||||||
else if (DTLBMissM & DTLBWriteM & ITLBMissF)begin
|
|
||||||
NextState = STATE_PTW_READY;
|
|
||||||
DCacheStall = 1'b0;
|
|
||||||
|
|
||||||
// read hit valid cached
|
|
||||||
end else if(MemRWM[1] & CacheableM & ~ExceptionM & CacheHit) begin
|
|
||||||
NextState = STATE_PTW_READY;
|
|
||||||
DCacheStall = 1'b0;
|
|
||||||
LRUWriteEn = 1'b1;
|
|
||||||
end
|
|
||||||
|
|
||||||
// read miss valid cached
|
|
||||||
else if(SelPTW & MemRWM[1] & CacheableM & ~ExceptionM & ~CacheHit) begin
|
|
||||||
NextState = STATE_PTW_READ_MISS_FETCH_WDV;
|
|
||||||
CntReset = 1'b1;
|
|
||||||
DCacheStall = 1'b1;
|
|
||||||
end
|
|
||||||
|
|
||||||
else begin
|
|
||||||
NextState = STATE_PTW_READY;
|
|
||||||
DCacheStall = 1'b0;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
STATE_PTW_READ_MISS_FETCH_WDV: begin
|
|
||||||
DCacheStall = 1'b1;
|
|
||||||
PreCntEn = 1'b1;
|
|
||||||
AHBRead = 1'b1;
|
|
||||||
SelAdrM = 2'b10;
|
|
||||||
CommittedM = 1'b1;
|
|
||||||
|
|
||||||
if(FetchCountFlag & AHBAck) begin
|
|
||||||
NextState = STATE_PTW_READ_MISS_FETCH_DONE;
|
|
||||||
end else begin
|
|
||||||
NextState = STATE_PTW_READ_MISS_FETCH_WDV;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
STATE_PTW_READ_MISS_FETCH_DONE: begin
|
|
||||||
DCacheStall = 1'b1;
|
|
||||||
SelAdrM = 2'b10;
|
|
||||||
CntReset = 1'b1;
|
|
||||||
CommittedM = 1'b1;
|
|
||||||
CntReset = 1'b1;
|
|
||||||
if(VictimDirty) begin
|
|
||||||
NextState = STATE_PTW_READ_MISS_EVICT_DIRTY;
|
|
||||||
end else begin
|
|
||||||
NextState = STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
STATE_PTW_READ_MISS_EVICT_DIRTY: begin
|
|
||||||
DCacheStall = 1'b1;
|
|
||||||
PreCntEn = 1'b1;
|
|
||||||
AHBWrite = 1'b1;
|
|
||||||
SelAdrM = 2'b10;
|
|
||||||
CommittedM = 1'b1;
|
|
||||||
SelEvict = 1'b1;
|
|
||||||
if(FetchCountFlag & AHBAck) begin
|
|
||||||
NextState = STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK;
|
|
||||||
end else begin
|
|
||||||
NextState = STATE_PTW_READ_MISS_EVICT_DIRTY;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
|
|
||||||
STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK: begin
|
|
||||||
SRAMBlockWriteEnableM = 1'b1;
|
|
||||||
DCacheStall = 1'b1;
|
|
||||||
NextState = STATE_PTW_READ_MISS_READ_WORD;
|
|
||||||
SelAdrM = 2'b10;
|
|
||||||
SetValid = 1'b1;
|
|
||||||
ClearDirty = 1'b1;
|
|
||||||
CommittedM = 1'b1;
|
|
||||||
//LRUWriteEn = 1'b1;
|
|
||||||
end
|
|
||||||
|
|
||||||
STATE_PTW_READ_MISS_READ_WORD: begin
|
|
||||||
SelAdrM = 2'b10;
|
|
||||||
DCacheStall = 1'b1;
|
|
||||||
CommittedM = 1'b1;
|
|
||||||
NextState = STATE_PTW_READ_MISS_READ_WORD_DELAY;
|
|
||||||
end
|
|
||||||
|
|
||||||
STATE_PTW_READ_MISS_READ_WORD_DELAY: begin
|
|
||||||
SelAdrM = 2'b10;
|
|
||||||
NextState = STATE_PTW_READY;
|
|
||||||
CommittedM = 1'b1;
|
|
||||||
end
|
|
||||||
|
|
||||||
STATE_PTW_ACCESS_AFTER_WALK: begin
|
|
||||||
DCacheStall = 1'b1;
|
|
||||||
SelAdrM = 2'b10;
|
|
||||||
CommittedM = 1'b1;
|
|
||||||
LRUWriteEn = 1'b1;
|
|
||||||
NextState = STATE_READY;
|
|
||||||
end
|
|
||||||
|
|
||||||
STATE_CPU_BUSY: begin
|
STATE_CPU_BUSY: begin
|
||||||
CommittedM = 1'b1;
|
CommittedM = 1'b1;
|
||||||
SelAdrM = 2'b00;
|
SelAdrM = 2'b00;
|
||||||
@ -608,249 +437,6 @@ module dcachefsm
|
|||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
||||||
// itlb => instruction page fault states with memory request.
|
|
||||||
STATE_PTW_FAULT_READY: begin
|
|
||||||
DCacheStall = 1'b0;
|
|
||||||
LRUWriteEn = 1'b0;
|
|
||||||
SelAdrM = 2'b00;
|
|
||||||
MemAfterIWalkDone = 1'b0;
|
|
||||||
SetDirty = 1'b0;
|
|
||||||
LRUWriteEn = 1'b0;
|
|
||||||
CntReset = 1'b0;
|
|
||||||
AHBWrite = 1'b0;
|
|
||||||
AHBRead = 1'b0;
|
|
||||||
CommittedM = 1'b1;
|
|
||||||
NextState = STATE_READY;
|
|
||||||
|
|
||||||
|
|
||||||
// read hit valid cached
|
|
||||||
if(MemRWM[1] & CacheableM & CacheHit & ~DTLBMissM) begin
|
|
||||||
DCacheStall = 1'b0;
|
|
||||||
LRUWriteEn = 1'b1;
|
|
||||||
|
|
||||||
if(StallWtoDCache) begin
|
|
||||||
NextState = STATE_PTW_FAULT_CPU_BUSY;
|
|
||||||
SelAdrM = 2'b10;
|
|
||||||
end
|
|
||||||
else begin
|
|
||||||
MemAfterIWalkDone = 1'b1;
|
|
||||||
NextState = STATE_READY;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
// write hit valid cached
|
|
||||||
else if (MemRWM[0] & CacheableM & CacheHit & ~DTLBMissM) begin
|
|
||||||
SelAdrM = 2'b10;
|
|
||||||
DCacheStall = 1'b0;
|
|
||||||
SRAMWordWriteEnableM = 1'b1;
|
|
||||||
SetDirty = 1'b1;
|
|
||||||
LRUWriteEn = 1'b1;
|
|
||||||
|
|
||||||
if(StallWtoDCache) begin
|
|
||||||
NextState = STATE_PTW_FAULT_CPU_BUSY;
|
|
||||||
SelAdrM = 2'b10;
|
|
||||||
end
|
|
||||||
else begin
|
|
||||||
MemAfterIWalkDone = 1'b1;
|
|
||||||
NextState = STATE_READY;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
// read or write miss valid cached
|
|
||||||
else if((|MemRWM) & CacheableM & ~CacheHit & ~DTLBMissM) begin
|
|
||||||
NextState = STATE_PTW_FAULT_MISS_FETCH_WDV;
|
|
||||||
CntReset = 1'b1;
|
|
||||||
DCacheStall = 1'b1;
|
|
||||||
end
|
|
||||||
// uncached write
|
|
||||||
else if(MemRWM[0] & ~CacheableM & ~DTLBMissM) begin
|
|
||||||
NextState = STATE_PTW_FAULT_UNCACHED_WRITE;
|
|
||||||
CntReset = 1'b1;
|
|
||||||
DCacheStall = 1'b1;
|
|
||||||
AHBWrite = 1'b1;
|
|
||||||
end
|
|
||||||
// uncached read
|
|
||||||
else if(MemRWM[1] & ~CacheableM & ~DTLBMissM) begin
|
|
||||||
NextState = STATE_PTW_FAULT_UNCACHED_READ;
|
|
||||||
CntReset = 1'b1;
|
|
||||||
DCacheStall = 1'b1;
|
|
||||||
AHBRead = 1'b1;
|
|
||||||
MemAfterIWalkDone = 1'b0;
|
|
||||||
end
|
|
||||||
// fault
|
|
||||||
else begin
|
|
||||||
MemAfterIWalkDone = 1'b1;
|
|
||||||
NextState = STATE_READY;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
STATE_PTW_FAULT_CPU_BUSY: begin
|
|
||||||
CommittedM = 1'b1;
|
|
||||||
if(StallWtoDCache) begin
|
|
||||||
NextState = STATE_PTW_FAULT_CPU_BUSY;
|
|
||||||
MemAfterIWalkDone = 1'b0;
|
|
||||||
SelAdrM = 2'b10;
|
|
||||||
end
|
|
||||||
else begin
|
|
||||||
MemAfterIWalkDone = 1'b1;
|
|
||||||
NextState = STATE_READY;
|
|
||||||
SelAdrM = 2'b00;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
STATE_PTW_FAULT_MISS_FETCH_WDV: begin
|
|
||||||
DCacheStall = 1'b1;
|
|
||||||
PreCntEn = 1'b1;
|
|
||||||
AHBRead = 1'b1;
|
|
||||||
SelAdrM = 2'b10;
|
|
||||||
CommittedM = 1'b1;
|
|
||||||
|
|
||||||
if(FetchCountFlag & AHBAck) begin
|
|
||||||
NextState = STATE_PTW_FAULT_MISS_FETCH_DONE;
|
|
||||||
end else begin
|
|
||||||
NextState = STATE_PTW_FAULT_MISS_FETCH_WDV;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
STATE_PTW_FAULT_MISS_FETCH_DONE: begin
|
|
||||||
DCacheStall = 1'b1;
|
|
||||||
SelAdrM = 2'b10;
|
|
||||||
CntReset = 1'b1;
|
|
||||||
CommittedM = 1'b1;
|
|
||||||
if(VictimDirty) begin
|
|
||||||
NextState = STATE_PTW_FAULT_MISS_EVICT_DIRTY;
|
|
||||||
end else begin
|
|
||||||
NextState = STATE_PTW_FAULT_MISS_WRITE_CACHE_BLOCK;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
STATE_PTW_FAULT_MISS_WRITE_CACHE_BLOCK: begin
|
|
||||||
SRAMBlockWriteEnableM = 1'b1;
|
|
||||||
DCacheStall = 1'b1;
|
|
||||||
NextState = STATE_PTW_FAULT_MISS_READ_WORD;
|
|
||||||
SelAdrM = 2'b10;
|
|
||||||
SetValid = 1'b1;
|
|
||||||
ClearDirty = 1'b1;
|
|
||||||
CommittedM = 1'b1;
|
|
||||||
//LRUWriteEn = 1'b1; // DO not update LRU on SRAM fetch update. Wait for subsequent read/write
|
|
||||||
end
|
|
||||||
|
|
||||||
STATE_PTW_FAULT_MISS_READ_WORD: begin
|
|
||||||
SelAdrM = 2'b10;
|
|
||||||
DCacheStall = 1'b1;
|
|
||||||
CommittedM = 1'b1;
|
|
||||||
if(MemRWM[1]) begin
|
|
||||||
NextState = STATE_PTW_FAULT_MISS_READ_WORD_DELAY;
|
|
||||||
// delay state is required as the read signal MemRWM[1] is still high when we
|
|
||||||
// return to the ready state because the cache is stalling the cpu.
|
|
||||||
end else begin
|
|
||||||
NextState = STATE_PTW_FAULT_MISS_WRITE_WORD;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
STATE_PTW_FAULT_MISS_READ_WORD_DELAY: begin
|
|
||||||
CommittedM = 1'b1;
|
|
||||||
LRUWriteEn = 1'b1;
|
|
||||||
if(StallWtoDCache) begin
|
|
||||||
NextState = STATE_PTW_FAULT_CPU_BUSY;
|
|
||||||
SelAdrM = 2'b10;
|
|
||||||
MemAfterIWalkDone = 1'b0;
|
|
||||||
end
|
|
||||||
else begin
|
|
||||||
MemAfterIWalkDone = 1'b1;
|
|
||||||
NextState = STATE_READY;
|
|
||||||
SelAdrM = 2'b00;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
STATE_PTW_FAULT_MISS_WRITE_WORD: begin
|
|
||||||
SRAMWordWriteEnableM = 1'b1;
|
|
||||||
SetDirty = 1'b1;
|
|
||||||
SelAdrM = 2'b10;
|
|
||||||
DCacheStall = 1'b1;
|
|
||||||
CommittedM = 1'b1;
|
|
||||||
LRUWriteEn = 1'b1;
|
|
||||||
NextState = STATE_PTW_FAULT_MISS_WRITE_WORD_DELAY;
|
|
||||||
end
|
|
||||||
|
|
||||||
STATE_PTW_FAULT_MISS_WRITE_WORD_DELAY: begin
|
|
||||||
CommittedM = 1'b1;
|
|
||||||
if(StallWtoDCache) begin
|
|
||||||
NextState = STATE_PTW_FAULT_CPU_BUSY;
|
|
||||||
MemAfterIWalkDone = 1'b0;
|
|
||||||
SelAdrM = 2'b10;
|
|
||||||
end
|
|
||||||
else begin
|
|
||||||
MemAfterIWalkDone = 1'b1;
|
|
||||||
NextState = STATE_READY;
|
|
||||||
SelAdrM = 2'b00;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
STATE_PTW_FAULT_MISS_EVICT_DIRTY: begin
|
|
||||||
DCacheStall = 1'b1;
|
|
||||||
PreCntEn = 1'b1;
|
|
||||||
AHBWrite = 1'b1;
|
|
||||||
SelAdrM = 2'b10;
|
|
||||||
CommittedM = 1'b1;
|
|
||||||
SelEvict = 1'b1;
|
|
||||||
if(FetchCountFlag & AHBAck) begin
|
|
||||||
NextState = STATE_PTW_FAULT_MISS_WRITE_CACHE_BLOCK;
|
|
||||||
end else begin
|
|
||||||
NextState = STATE_PTW_FAULT_MISS_EVICT_DIRTY;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
|
|
||||||
STATE_PTW_FAULT_UNCACHED_WRITE : begin
|
|
||||||
DCacheStall = 1'b1;
|
|
||||||
AHBWrite = 1'b1;
|
|
||||||
CommittedM = 1'b1;
|
|
||||||
if(AHBAck) begin
|
|
||||||
NextState = STATE_PTW_FAULT_UNCACHED_WRITE_DONE;
|
|
||||||
end else begin
|
|
||||||
NextState = STATE_PTW_FAULT_UNCACHED_WRITE;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
STATE_PTW_FAULT_UNCACHED_READ : begin
|
|
||||||
DCacheStall = 1'b1;
|
|
||||||
AHBRead = 1'b1;
|
|
||||||
CommittedM = 1'b1;
|
|
||||||
if(AHBAck) begin
|
|
||||||
NextState = STATE_PTW_FAULT_UNCACHED_READ_DONE;
|
|
||||||
end else begin
|
|
||||||
NextState = STATE_PTW_FAULT_UNCACHED_READ;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
STATE_PTW_FAULT_UNCACHED_WRITE_DONE: begin
|
|
||||||
CommittedM = 1'b1;
|
|
||||||
if(StallWtoDCache) begin
|
|
||||||
NextState = STATE_PTW_FAULT_CPU_BUSY;
|
|
||||||
MemAfterIWalkDone = 1'b0;
|
|
||||||
SelAdrM = 2'b10;
|
|
||||||
end
|
|
||||||
else begin
|
|
||||||
MemAfterIWalkDone = 1'b1;
|
|
||||||
NextState = STATE_READY;
|
|
||||||
SelAdrM = 2'b00;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
STATE_PTW_FAULT_UNCACHED_READ_DONE: begin
|
|
||||||
CommittedM = 1'b1;
|
|
||||||
SelUncached = 1'b1;
|
|
||||||
if(StallWtoDCache) begin
|
|
||||||
NextState = STATE_PTW_FAULT_CPU_BUSY;
|
|
||||||
SelAdrM = 2'b10;
|
|
||||||
end
|
|
||||||
else begin
|
|
||||||
MemAfterIWalkDone = 1'b1;
|
|
||||||
NextState = STATE_READY;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
STATE_FLUSH: begin
|
STATE_FLUSH: begin
|
||||||
DCacheStall = 1'b1;
|
DCacheStall = 1'b1;
|
||||||
CommittedM = 1'b1;
|
CommittedM = 1'b1;
|
||||||
|
|||||||
5
wally-pipelined/src/cache/icache.sv
vendored
5
wally-pipelined/src/cache/icache.sv
vendored
@ -32,6 +32,7 @@ module icache
|
|||||||
input logic StallF,
|
input logic StallF,
|
||||||
input logic [`PA_BITS-1:0] PCNextF,
|
input logic [`PA_BITS-1:0] PCNextF,
|
||||||
input logic [`PA_BITS-1:0] PCPF,
|
input logic [`PA_BITS-1:0] PCPF,
|
||||||
|
input logic [`XLEN-1:0] PCF,
|
||||||
|
|
||||||
input logic ExceptionM, PendingInterruptM,
|
input logic ExceptionM, PendingInterruptM,
|
||||||
|
|
||||||
@ -125,7 +126,7 @@ module icache
|
|||||||
|
|
||||||
mux3 #(INDEXLEN)
|
mux3 #(INDEXLEN)
|
||||||
AdrSelMux(.d0(PCNextF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
|
AdrSelMux(.d0(PCNextF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
|
||||||
.d1(PCPF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
|
.d1(PCF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
|
||||||
.d2(PCPSpillF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
|
.d2(PCPSpillF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
|
||||||
.s(SelAdr),
|
.s(SelAdr),
|
||||||
.y(RAdr));
|
.y(RAdr));
|
||||||
@ -219,7 +220,7 @@ module icache
|
|||||||
|
|
||||||
// Detect if the instruction is compressed
|
// Detect if the instruction is compressed
|
||||||
assign CompressedF = FinalInstrRawF[1:0] != 2'b11;
|
assign CompressedF = FinalInstrRawF[1:0] != 2'b11;
|
||||||
assign spill = PCPF[4:1] == 4'b1111 ? 1'b1 : 1'b0;
|
assign spill = PCF[4:1] == 4'b1111 ? 1'b1 : 1'b0;
|
||||||
|
|
||||||
|
|
||||||
// to compute the fetch address we need to add the bit shifted
|
// to compute the fetch address we need to add the bit shifted
|
||||||
|
|||||||
22
wally-pipelined/src/cache/icachefsm.sv
vendored
22
wally-pipelined/src/cache/icachefsm.sv
vendored
@ -137,9 +137,17 @@ module icachefsm
|
|||||||
STATE_READY: begin
|
STATE_READY: begin
|
||||||
SelAdr = 2'b00;
|
SelAdr = 2'b00;
|
||||||
ICacheReadEn = 1'b1;
|
ICacheReadEn = 1'b1;
|
||||||
|
/* -----\/----- EXCLUDED -----\/-----
|
||||||
if (ITLBMissF & ~(ExceptionM | PendingInterruptM)) begin
|
if (ITLBMissF & ~(ExceptionM | PendingInterruptM)) begin
|
||||||
NextState = STATE_TLB_MISS;
|
NextState = STATE_TLB_MISS;
|
||||||
end else if (hit & ~spill) begin
|
end else
|
||||||
|
-----/\----- EXCLUDED -----/\----- */
|
||||||
|
if(ITLBMissF) begin
|
||||||
|
NextState = STATE_READY;
|
||||||
|
SelAdr = 2'b01;
|
||||||
|
ICacheStallF = 1'b0;
|
||||||
|
end
|
||||||
|
else if (hit & ~spill) begin
|
||||||
ICacheStallF = 1'b0;
|
ICacheStallF = 1'b0;
|
||||||
LRUWriteEn = 1'b1;
|
LRUWriteEn = 1'b1;
|
||||||
if(StallF) begin
|
if(StallF) begin
|
||||||
@ -325,6 +333,7 @@ module icachefsm
|
|||||||
NextState = STATE_READY;
|
NextState = STATE_READY;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
/* -----\/----- EXCLUDED -----\/-----
|
||||||
STATE_TLB_MISS: begin
|
STATE_TLB_MISS: begin
|
||||||
if (WalkerInstrPageFaultF) begin
|
if (WalkerInstrPageFaultF) begin
|
||||||
NextState = STATE_READY;
|
NextState = STATE_READY;
|
||||||
@ -341,11 +350,15 @@ module icachefsm
|
|||||||
SelAdr = 2'b01;
|
SelAdr = 2'b01;
|
||||||
NextState = STATE_READY;
|
NextState = STATE_READY;
|
||||||
end
|
end
|
||||||
|
-----/\----- EXCLUDED -----/\----- */
|
||||||
STATE_CPU_BUSY: begin
|
STATE_CPU_BUSY: begin
|
||||||
ICacheStallF = 1'b0;
|
ICacheStallF = 1'b0;
|
||||||
|
/* -----\/----- EXCLUDED -----\/-----
|
||||||
if (ITLBMissF) begin
|
if (ITLBMissF) begin
|
||||||
NextState = STATE_TLB_MISS;
|
NextState = STATE_TLB_MISS;
|
||||||
end else if(StallF) begin
|
end else
|
||||||
|
-----/\----- EXCLUDED -----/\----- */
|
||||||
|
if(StallF) begin
|
||||||
NextState = STATE_CPU_BUSY;
|
NextState = STATE_CPU_BUSY;
|
||||||
SelAdr = 2'b01;
|
SelAdr = 2'b01;
|
||||||
end
|
end
|
||||||
@ -356,9 +369,12 @@ module icachefsm
|
|||||||
STATE_CPU_BUSY_SPILL: begin
|
STATE_CPU_BUSY_SPILL: begin
|
||||||
ICacheStallF = 1'b0;
|
ICacheStallF = 1'b0;
|
||||||
ICacheReadEn = 1'b1;
|
ICacheReadEn = 1'b1;
|
||||||
|
/* -----\/----- EXCLUDED -----\/-----
|
||||||
if (ITLBMissF) begin
|
if (ITLBMissF) begin
|
||||||
NextState = STATE_TLB_MISS;
|
NextState = STATE_TLB_MISS;
|
||||||
end else if(StallF) begin
|
end else
|
||||||
|
-----/\----- EXCLUDED -----/\----- */
|
||||||
|
if(StallF) begin
|
||||||
NextState = STATE_CPU_BUSY_SPILL;
|
NextState = STATE_CPU_BUSY_SPILL;
|
||||||
SelAdr = 2'b10;
|
SelAdr = 2'b10;
|
||||||
end
|
end
|
||||||
|
|||||||
@ -168,6 +168,7 @@ module ifu (
|
|||||||
|
|
||||||
.PCNextF(PCNextFPhys),
|
.PCNextF(PCNextFPhys),
|
||||||
.PCPF(PCPFmmu),
|
.PCPF(PCPFmmu),
|
||||||
|
.PCF,
|
||||||
.WalkerInstrPageFaultF,
|
.WalkerInstrPageFaultF,
|
||||||
.InvalidateICacheM);
|
.InvalidateICacheM);
|
||||||
|
|
||||||
|
|||||||
@ -50,7 +50,7 @@ module lsu
|
|||||||
|
|
||||||
// address and write data
|
// address and write data
|
||||||
input logic [`XLEN-1:0] IEUAdrE,
|
input logic [`XLEN-1:0] IEUAdrE,
|
||||||
output logic [`XLEN-1:0] MemAdrM,
|
output logic [`XLEN-1:0] IEUAdrM,
|
||||||
input logic [`XLEN-1:0] WriteDataM,
|
input logic [`XLEN-1:0] WriteDataM,
|
||||||
output logic [`XLEN-1:0] ReadDataM,
|
output logic [`XLEN-1:0] ReadDataM,
|
||||||
|
|
||||||
@ -107,8 +107,8 @@ module lsu
|
|||||||
logic [1:0] MemRWMtoLRSC;
|
logic [1:0] MemRWMtoLRSC;
|
||||||
logic [2:0] Funct3MtoDCache;
|
logic [2:0] Funct3MtoDCache;
|
||||||
logic [1:0] AtomicMtoDCache;
|
logic [1:0] AtomicMtoDCache;
|
||||||
logic [`PA_BITS-1:0] MemPAdrMtoDCache;
|
logic [`PA_BITS-1:0] MemPAdrNoTranslate;
|
||||||
logic [11:0] MemAdrEtoDCache;
|
logic [11:0] MemAdrE, MemAdrE_RENAME;
|
||||||
logic StallWtoDCache;
|
logic StallWtoDCache;
|
||||||
logic MemReadM;
|
logic MemReadM;
|
||||||
logic DataMisalignedMfromDCache;
|
logic DataMisalignedMfromDCache;
|
||||||
@ -127,9 +127,132 @@ module lsu
|
|||||||
logic AnyCPUReqM;
|
logic AnyCPUReqM;
|
||||||
logic MemAfterIWalkDone;
|
logic MemAfterIWalkDone;
|
||||||
|
|
||||||
|
typedef enum {STATE_T0_READY,
|
||||||
|
STATE_T0_REPLAY,
|
||||||
|
STATE_T0_FAULT_REPLAY,
|
||||||
|
STATE_T3_DTLB_MISS,
|
||||||
|
STATE_T4_ITLB_MISS,
|
||||||
|
STATE_T5_ITLB_MISS,
|
||||||
|
STATE_T7_DITLB_MISS} statetype;
|
||||||
|
|
||||||
|
statetype CurrState, NextState;
|
||||||
|
logic InterlockStall;
|
||||||
|
logic SelReplayCPURequest;
|
||||||
|
logic WalkerInstrPageFaultRaw;
|
||||||
|
logic IgnoreRequest;
|
||||||
|
|
||||||
|
|
||||||
assign AnyCPUReqM = (|MemRWM) | (|AtomicM);
|
assign AnyCPUReqM = (|MemRWM) | (|AtomicM);
|
||||||
|
|
||||||
flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, MemAdrM);
|
always_ff @(posedge clk)
|
||||||
|
if (reset) CurrState <= #1 STATE_T0_READY;
|
||||||
|
else CurrState <= #1 NextState;
|
||||||
|
|
||||||
|
always_comb begin
|
||||||
|
case(CurrState)
|
||||||
|
STATE_T0_READY: begin
|
||||||
|
if(~ITLBMissF & DTLBMissM & AnyCPUReqM) begin
|
||||||
|
NextState = STATE_T3_DTLB_MISS;
|
||||||
|
end
|
||||||
|
else if(ITLBMissF & ~DTLBMissM & ~AnyCPUReqM) begin
|
||||||
|
NextState = STATE_T4_ITLB_MISS;
|
||||||
|
end
|
||||||
|
else if(ITLBMissF & ~DTLBMissM & AnyCPUReqM) begin
|
||||||
|
NextState = STATE_T5_ITLB_MISS;
|
||||||
|
end
|
||||||
|
else if(ITLBMissF & DTLBMissM & AnyCPUReqM) begin
|
||||||
|
NextState = STATE_T7_DITLB_MISS;
|
||||||
|
end else begin
|
||||||
|
NextState = STATE_T0_READY;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
STATE_T0_REPLAY: begin
|
||||||
|
if(DCacheStall) begin
|
||||||
|
NextState = STATE_T0_REPLAY;
|
||||||
|
end else begin
|
||||||
|
NextState = STATE_T0_READY;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
STATE_T3_DTLB_MISS: begin
|
||||||
|
if(WalkerLoadPageFaultM | WalkerStorePageFaultM) begin
|
||||||
|
NextState = STATE_T0_READY;
|
||||||
|
end else if(DTLBWriteM) begin
|
||||||
|
NextState = STATE_T0_REPLAY;
|
||||||
|
end else begin
|
||||||
|
NextState = STATE_T3_DTLB_MISS;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
STATE_T4_ITLB_MISS: begin
|
||||||
|
if(WalkerInstrPageFaultRaw | ITLBWriteF) begin
|
||||||
|
NextState = STATE_T0_READY;
|
||||||
|
end else begin
|
||||||
|
NextState = STATE_T4_ITLB_MISS;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
STATE_T5_ITLB_MISS: begin
|
||||||
|
if(ITLBWriteF) begin
|
||||||
|
NextState = STATE_T0_REPLAY;
|
||||||
|
end else if(WalkerInstrPageFaultRaw) begin
|
||||||
|
NextState = STATE_T0_FAULT_REPLAY;
|
||||||
|
end else begin
|
||||||
|
NextState = STATE_T5_ITLB_MISS;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
STATE_T0_FAULT_REPLAY: begin
|
||||||
|
if(DCacheStall) begin
|
||||||
|
NextState = STATE_T0_FAULT_REPLAY;
|
||||||
|
end else begin
|
||||||
|
NextState = STATE_T0_READY;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
STATE_T7_DITLB_MISS: begin
|
||||||
|
if(WalkerStorePageFaultM | WalkerLoadPageFaultM) begin
|
||||||
|
NextState = STATE_T0_READY;
|
||||||
|
end else if(DTLBWriteM) begin
|
||||||
|
NextState = STATE_T5_ITLB_MISS;
|
||||||
|
end else begin
|
||||||
|
NextState = STATE_T7_DITLB_MISS;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
default: begin
|
||||||
|
NextState = STATE_T0_READY;
|
||||||
|
end
|
||||||
|
endcase
|
||||||
|
end // always_comb
|
||||||
|
|
||||||
|
// signal to CPU it needs to wait on HPTW.
|
||||||
|
/* -----\/----- EXCLUDED -----\/-----
|
||||||
|
// this code has a problem with imperas64mmu as it reads in an invalid uninitalized instruction. InterlockStall becomes x and it propagates
|
||||||
|
// everywhere. The case statement below implements the same logic but any x on the inputs will resolve to 0.
|
||||||
|
assign InterlockStall = (CurrState == STATE_T0_READY & (DTLBMissM | ITLBMissF)) |
|
||||||
|
(CurrState == STATE_T3_DTLB_MISS & ~WalkerPageFaultM) | (CurrState == STATE_T4_ITLB_MISS & ~WalkerInstrPageFaultRaw) |
|
||||||
|
(CurrState == STATE_T5_ITLB_MISS & ~WalkerInstrPageFaultRaw) | (CurrState == STATE_T7_DITLB_MISS & ~WalkerPageFaultM);
|
||||||
|
|
||||||
|
-----/\----- EXCLUDED -----/\----- */
|
||||||
|
|
||||||
|
always_comb begin
|
||||||
|
InterlockStall = 1'b0;
|
||||||
|
case(CurrState)
|
||||||
|
STATE_T0_READY: if(DTLBMissM | ITLBMissF) InterlockStall = 1'b1;
|
||||||
|
STATE_T3_DTLB_MISS: if (~WalkerPageFaultM) InterlockStall = 1'b1;
|
||||||
|
STATE_T4_ITLB_MISS: if (~WalkerInstrPageFaultRaw) InterlockStall = 1'b1;
|
||||||
|
STATE_T5_ITLB_MISS: if (~WalkerInstrPageFaultRaw) InterlockStall = 1'b1;
|
||||||
|
STATE_T7_DITLB_MISS: if (~WalkerPageFaultM) InterlockStall = 1'b1;
|
||||||
|
default: InterlockStall = 1'b0;
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
|
||||||
|
|
||||||
|
// When replaying CPU memory request after PTW select the IEUAdrM for correct address.
|
||||||
|
assign SelReplayCPURequest = NextState == STATE_T0_REPLAY;
|
||||||
|
assign SelPTW = (CurrState == STATE_T3_DTLB_MISS) | (CurrState == STATE_T4_ITLB_MISS) |
|
||||||
|
(CurrState == STATE_T5_ITLB_MISS) | (CurrState == STATE_T7_DITLB_MISS);
|
||||||
|
assign IgnoreRequest = CurrState == STATE_T0_READY & (ITLBMissF | DTLBMissM);
|
||||||
|
|
||||||
|
assign WalkerInstrPageFaultF = WalkerInstrPageFaultRaw | CurrState == STATE_T0_FAULT_REPLAY;
|
||||||
|
|
||||||
|
|
||||||
|
flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM);
|
||||||
|
|
||||||
// *** add generate to conditionally create hptw, lsuArb, and mmu
|
// *** add generate to conditionally create hptw, lsuArb, and mmu
|
||||||
// based on `MEM_VIRTMEM
|
// based on `MEM_VIRTMEM
|
||||||
@ -137,7 +260,7 @@ module lsu
|
|||||||
.reset(reset),
|
.reset(reset),
|
||||||
.SATP_REGW(SATP_REGW),
|
.SATP_REGW(SATP_REGW),
|
||||||
.PCF(PCF),
|
.PCF(PCF),
|
||||||
.MemAdrM(MemAdrM),
|
.IEUAdrM(IEUAdrM),
|
||||||
.ITLBMissF(ITLBMissF & ~PendingInterruptM),
|
.ITLBMissF(ITLBMissF & ~PendingInterruptM),
|
||||||
.DTLBMissM(DTLBMissM & ~PendingInterruptM),
|
.DTLBMissM(DTLBMissM & ~PendingInterruptM),
|
||||||
.MemRWM(MemRWM),
|
.MemRWM(MemRWM),
|
||||||
@ -146,44 +269,43 @@ module lsu
|
|||||||
.ITLBWriteF(ITLBWriteF),
|
.ITLBWriteF(ITLBWriteF),
|
||||||
.DTLBWriteM(DTLBWriteM),
|
.DTLBWriteM(DTLBWriteM),
|
||||||
.HPTWReadPTE(ReadDataM),
|
.HPTWReadPTE(ReadDataM),
|
||||||
.HPTWStall(HPTWStall),
|
.DCacheStall(DCacheStall),
|
||||||
.TranslationPAdr,
|
.TranslationPAdr,
|
||||||
.HPTWRead(HPTWRead),
|
.HPTWRead(HPTWRead),
|
||||||
.SelPTW(SelPTW),
|
.HPTWStall,
|
||||||
.AnyCPUReqM,
|
.AnyCPUReqM,
|
||||||
.MemAfterIWalkDone,
|
.MemAfterIWalkDone,
|
||||||
.WalkerInstrPageFaultF(WalkerInstrPageFaultF),
|
.WalkerInstrPageFaultF(WalkerInstrPageFaultRaw),
|
||||||
.WalkerLoadPageFaultM(WalkerLoadPageFaultM),
|
.WalkerLoadPageFaultM(WalkerLoadPageFaultM),
|
||||||
.WalkerStorePageFaultM(WalkerStorePageFaultM));
|
.WalkerStorePageFaultM(WalkerStorePageFaultM));
|
||||||
|
|
||||||
|
assign LSUStall = DCacheStall | InterlockStall;
|
||||||
|
|
||||||
assign WalkerPageFaultM = WalkerStorePageFaultM | WalkerLoadPageFaultM;
|
assign WalkerPageFaultM = WalkerStorePageFaultM | WalkerLoadPageFaultM;
|
||||||
|
|
||||||
// arbiter between IEU and hptw
|
// arbiter between IEU and hptw
|
||||||
lsuArb arbiter(.clk(clk),
|
lsuArb arbiter(.clk(clk),
|
||||||
// HPTW connection
|
// HPTW connection
|
||||||
.SelPTW(SelPTW),
|
.SelPTW,
|
||||||
.HPTWRead(HPTWRead),
|
.HPTWRead(HPTWRead),
|
||||||
.TranslationPAdrE(TranslationPAdr),
|
.TranslationPAdrE(TranslationPAdr),
|
||||||
.HPTWStall(HPTWStall),
|
|
||||||
// CPU connection
|
// CPU connection
|
||||||
.MemRWM(MemRWM),
|
.MemRWM(MemRWM),
|
||||||
.Funct3M(Funct3M),
|
.Funct3M(Funct3M),
|
||||||
.AtomicM(AtomicM),
|
.AtomicM(AtomicM),
|
||||||
.MemAdrM(MemAdrM),
|
.IEUAdrM(IEUAdrM),
|
||||||
.IEUAdrE(IEUAdrE[11:0]),
|
.IEUAdrE(IEUAdrE[11:0]),
|
||||||
.CommittedM(CommittedM),
|
.CommittedM(CommittedM),
|
||||||
.PendingInterruptM(PendingInterruptM),
|
.PendingInterruptM(PendingInterruptM),
|
||||||
.StallW(StallW),
|
.StallW(StallW),
|
||||||
.DataMisalignedM(DataMisalignedM),
|
.DataMisalignedM(DataMisalignedM),
|
||||||
.LSUStall(LSUStall),
|
|
||||||
// DCACHE
|
// DCACHE
|
||||||
.DisableTranslation(DisableTranslation),
|
.DisableTranslation(DisableTranslation),
|
||||||
.MemRWMtoLRSC(MemRWMtoLRSC),
|
.MemRWMtoLRSC(MemRWMtoLRSC),
|
||||||
.Funct3MtoDCache(Funct3MtoDCache),
|
.Funct3MtoDCache(Funct3MtoDCache),
|
||||||
.AtomicMtoDCache(AtomicMtoDCache),
|
.AtomicMtoDCache(AtomicMtoDCache),
|
||||||
.MemPAdrMtoDCache(MemPAdrMtoDCache),
|
.MemPAdrNoTranslate(MemPAdrNoTranslate),
|
||||||
.MemAdrEtoDCache(MemAdrEtoDCache),
|
.MemAdrE(MemAdrE),
|
||||||
.StallWtoDCache(StallWtoDCache),
|
.StallWtoDCache(StallWtoDCache),
|
||||||
.DataMisalignedMfromDCache(DataMisalignedMfromDCache),
|
.DataMisalignedMfromDCache(DataMisalignedMfromDCache),
|
||||||
.CommittedMfromDCache(CommittedMfromDCache),
|
.CommittedMfromDCache(CommittedMfromDCache),
|
||||||
@ -193,8 +315,8 @@ module lsu
|
|||||||
mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0))
|
mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0))
|
||||||
dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
|
dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
|
||||||
.PrivilegeModeW, .DisableTranslation(DisableTranslation),
|
.PrivilegeModeW, .DisableTranslation(DisableTranslation),
|
||||||
.PAdr(MemPAdrMtoDCache),
|
.PAdr(MemPAdrNoTranslate),
|
||||||
.VAdr(MemAdrM),
|
.VAdr(IEUAdrM),
|
||||||
.Size(Funct3MtoDCache[1:0]),
|
.Size(Funct3MtoDCache[1:0]),
|
||||||
.PTE(PTE),
|
.PTE(PTE),
|
||||||
.PageTypeWriteVal(PageType),
|
.PageTypeWriteVal(PageType),
|
||||||
@ -232,9 +354,9 @@ module lsu
|
|||||||
always_comb
|
always_comb
|
||||||
case(Funct3MtoDCache[1:0])
|
case(Funct3MtoDCache[1:0])
|
||||||
2'b00: DataMisalignedMfromDCache = 0; // lb, sb, lbu
|
2'b00: DataMisalignedMfromDCache = 0; // lb, sb, lbu
|
||||||
2'b01: DataMisalignedMfromDCache = MemPAdrMtoDCache[0]; // lh, sh, lhu
|
2'b01: DataMisalignedMfromDCache = MemPAdrNoTranslate[0]; // lh, sh, lhu
|
||||||
2'b10: DataMisalignedMfromDCache = MemPAdrMtoDCache[1] | MemPAdrMtoDCache[0]; // lw, sw, flw, fsw, lwu
|
2'b10: DataMisalignedMfromDCache = MemPAdrNoTranslate[1] | MemPAdrNoTranslate[0]; // lw, sw, flw, fsw, lwu
|
||||||
2'b11: DataMisalignedMfromDCache = |MemPAdrMtoDCache[2:0]; // ld, sd, fld, fsd
|
2'b11: DataMisalignedMfromDCache = |MemPAdrNoTranslate[2:0]; // ld, sd, fld, fsd
|
||||||
endcase
|
endcase
|
||||||
|
|
||||||
// Determine if address is valid
|
// Determine if address is valid
|
||||||
@ -245,6 +367,8 @@ module lsu
|
|||||||
// 1. ram // controlled by `MEM_DTIM
|
// 1. ram // controlled by `MEM_DTIM
|
||||||
// 2. cache `MEM_DCACHE
|
// 2. cache `MEM_DCACHE
|
||||||
// 3. wire pass-through
|
// 3. wire pass-through
|
||||||
|
assign MemAdrE_RENAME = SelReplayCPURequest ? IEUAdrM[11:0] : MemAdrE[11:0];
|
||||||
|
|
||||||
dcache dcache(.clk(clk),
|
dcache dcache(.clk(clk),
|
||||||
.reset(reset),
|
.reset(reset),
|
||||||
.StallWtoDCache(StallWtoDCache),
|
.StallWtoDCache(StallWtoDCache),
|
||||||
@ -253,9 +377,9 @@ module lsu
|
|||||||
.Funct7M(Funct7M),
|
.Funct7M(Funct7M),
|
||||||
.FlushDCacheM,
|
.FlushDCacheM,
|
||||||
.AtomicM(AtomicMtoDCache),
|
.AtomicM(AtomicMtoDCache),
|
||||||
.IEUAdrE(MemAdrEtoDCache),
|
.MemAdrE(MemAdrE_RENAME),
|
||||||
.MemPAdrM(MemPAdrM),
|
.MemPAdrM(MemPAdrM),
|
||||||
.VAdr(MemAdrM[11:0]),
|
.VAdr(IEUAdrM[11:0]), // this will be removed once the dcache hptw interlock is removed.
|
||||||
.WriteDataM(WriteDataM),
|
.WriteDataM(WriteDataM),
|
||||||
.ReadDataM(ReadDataM),
|
.ReadDataM(ReadDataM),
|
||||||
.DCacheStall(DCacheStall),
|
.DCacheStall(DCacheStall),
|
||||||
@ -263,16 +387,10 @@ module lsu
|
|||||||
.DCacheMiss,
|
.DCacheMiss,
|
||||||
.DCacheAccess,
|
.DCacheAccess,
|
||||||
.ExceptionM(ExceptionM),
|
.ExceptionM(ExceptionM),
|
||||||
|
.IgnoreRequest,
|
||||||
.PendingInterruptM(PendingInterruptMtoDCache),
|
.PendingInterruptM(PendingInterruptMtoDCache),
|
||||||
.DTLBMissM(DTLBMissM),
|
|
||||||
.CacheableM(CacheableMtoDCache),
|
.CacheableM(CacheableMtoDCache),
|
||||||
.DTLBWriteM(DTLBWriteM),
|
|
||||||
.ITLBWriteF(ITLBWriteF),
|
|
||||||
.ITLBMissF,
|
|
||||||
.MemAfterIWalkDone,
|
.MemAfterIWalkDone,
|
||||||
.SelPTW(SelPTW),
|
|
||||||
.WalkerPageFaultM(WalkerPageFaultM),
|
|
||||||
.WalkerInstrPageFaultF(WalkerInstrPageFaultF),
|
|
||||||
|
|
||||||
// AHB connection
|
// AHB connection
|
||||||
.AHBPAdr(DCtoAHBPAdrM),
|
.AHBPAdr(DCtoAHBPAdrM),
|
||||||
|
|||||||
@ -33,28 +33,27 @@ module lsuArb
|
|||||||
input logic SelPTW,
|
input logic SelPTW,
|
||||||
input logic HPTWRead,
|
input logic HPTWRead,
|
||||||
input logic [`PA_BITS-1:0] TranslationPAdrE,
|
input logic [`PA_BITS-1:0] TranslationPAdrE,
|
||||||
output logic HPTWStall,
|
|
||||||
|
|
||||||
// from CPU
|
// from CPU
|
||||||
input logic [1:0] MemRWM,
|
input logic [1:0] MemRWM,
|
||||||
input logic [2:0] Funct3M,
|
input logic [2:0] Funct3M,
|
||||||
input logic [1:0] AtomicM,
|
input logic [1:0] AtomicM,
|
||||||
input logic [`XLEN-1:0] MemAdrM,
|
input logic [`XLEN-1:0] IEUAdrM,
|
||||||
input logic [11:0] IEUAdrE,
|
input logic [11:0] IEUAdrE,
|
||||||
input logic StallW,
|
input logic StallW,
|
||||||
input logic PendingInterruptM,
|
input logic PendingInterruptM,
|
||||||
// to CPU
|
// to CPU
|
||||||
output logic DataMisalignedM,
|
output logic DataMisalignedM,
|
||||||
output logic CommittedM,
|
output logic CommittedM,
|
||||||
output logic LSUStall,
|
//output logic LSUStall,
|
||||||
|
|
||||||
// to D Cache
|
// to D Cache
|
||||||
output logic DisableTranslation,
|
output logic DisableTranslation,
|
||||||
output logic [1:0] MemRWMtoLRSC,
|
output logic [1:0] MemRWMtoLRSC,
|
||||||
output logic [2:0] Funct3MtoDCache,
|
output logic [2:0] Funct3MtoDCache,
|
||||||
output logic [1:0] AtomicMtoDCache,
|
output logic [1:0] AtomicMtoDCache,
|
||||||
output logic [`PA_BITS-1:0] MemPAdrMtoDCache,
|
output logic [`PA_BITS-1:0] MemPAdrNoTranslate, // THis name is very bad. need a better name. This is the raw address from either the ieu or the hptw.
|
||||||
output logic [11:0] MemAdrEtoDCache,
|
output logic [11:0] MemAdrE,
|
||||||
output logic StallWtoDCache,
|
output logic StallWtoDCache,
|
||||||
output logic PendingInterruptMtoDCache,
|
output logic PendingInterruptMtoDCache,
|
||||||
|
|
||||||
@ -68,7 +67,7 @@ module lsuArb
|
|||||||
|
|
||||||
logic [2:0] PTWSize;
|
logic [2:0] PTWSize;
|
||||||
logic [`PA_BITS-1:0] TranslationPAdrM;
|
logic [`PA_BITS-1:0] TranslationPAdrM;
|
||||||
logic [`XLEN+1:0] MemAdrMExt;
|
logic [`XLEN+1:0] IEUAdrMExt;
|
||||||
|
|
||||||
// multiplex the outputs to LSU
|
// multiplex the outputs to LSU
|
||||||
assign DisableTranslation = SelPTW; // change names between SelPTW would be confusing in DTLB.
|
assign DisableTranslation = SelPTW; // change names between SelPTW would be confusing in DTLB.
|
||||||
@ -83,9 +82,9 @@ module lsuArb
|
|||||||
flop #(`PA_BITS) TranslationPAdrMReg(clk, TranslationPAdrE, TranslationPAdrM); // delay TranslationPAdrM by a cycle
|
flop #(`PA_BITS) TranslationPAdrMReg(clk, TranslationPAdrE, TranslationPAdrM); // delay TranslationPAdrM by a cycle
|
||||||
|
|
||||||
assign AtomicMtoDCache = SelPTW ? 2'b00 : AtomicM;
|
assign AtomicMtoDCache = SelPTW ? 2'b00 : AtomicM;
|
||||||
assign MemAdrMExt = {2'b00, MemAdrM};
|
assign IEUAdrMExt = {2'b00, IEUAdrM};
|
||||||
assign MemPAdrMtoDCache = SelPTW ? TranslationPAdrM : MemAdrMExt[`PA_BITS-1:0];
|
assign MemPAdrNoTranslate = SelPTW ? TranslationPAdrM : IEUAdrMExt[`PA_BITS-1:0];
|
||||||
assign MemAdrEtoDCache = SelPTW ? TranslationPAdrE[11:0] : IEUAdrE[11:0];
|
assign MemAdrE = SelPTW ? TranslationPAdrE[11:0] : IEUAdrE[11:0];
|
||||||
assign StallWtoDCache = SelPTW ? 1'b0 : StallW;
|
assign StallWtoDCache = SelPTW ? 1'b0 : StallW;
|
||||||
// always block interrupts when using the hardware page table walker.
|
// always block interrupts when using the hardware page table walker.
|
||||||
assign CommittedM = SelPTW ? 1'b1 : CommittedMfromDCache;
|
assign CommittedM = SelPTW ? 1'b1 : CommittedMfromDCache;
|
||||||
@ -98,10 +97,9 @@ module lsuArb
|
|||||||
// not clear at all. I think it should be LSUStall from the LSU,
|
// not clear at all. I think it should be LSUStall from the LSU,
|
||||||
// which is demuxed to HPTWStall and CPUDataStall? (not sure on this last one).
|
// which is demuxed to HPTWStall and CPUDataStall? (not sure on this last one).
|
||||||
//assign HPTWStall = SelPTW ? DCacheStall : 1'b1;
|
//assign HPTWStall = SelPTW ? DCacheStall : 1'b1;
|
||||||
assign HPTWStall = DCacheStall;
|
|
||||||
|
|
||||||
assign PendingInterruptMtoDCache = SelPTW ? 1'b0 : PendingInterruptM;
|
assign PendingInterruptMtoDCache = SelPTW ? 1'b0 : PendingInterruptM;
|
||||||
|
|
||||||
assign LSUStall = SelPTW ? 1'b1 : DCacheStall; // *** this is probably going to change.
|
//assign LSUStall = SelPTW ? 1'b1 : DCacheStall; // *** this is probably going to change.
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
|||||||
@ -34,17 +34,17 @@ module hptw
|
|||||||
(
|
(
|
||||||
input logic clk, reset,
|
input logic clk, reset,
|
||||||
input logic [`XLEN-1:0] SATP_REGW, // includes SATP.MODE to determine number of levels in page table
|
input logic [`XLEN-1:0] SATP_REGW, // includes SATP.MODE to determine number of levels in page table
|
||||||
input logic [`XLEN-1:0] PCF, MemAdrM, // addresses to translate
|
input logic [`XLEN-1:0] PCF, IEUAdrM, // addresses to translate
|
||||||
input logic ITLBMissF, DTLBMissM, // TLB Miss
|
input logic ITLBMissF, DTLBMissM, // TLB Miss
|
||||||
input logic [1:0] MemRWM, // 10 = read, 01 = write
|
input logic [1:0] MemRWM, // 10 = read, 01 = write
|
||||||
input logic [`XLEN-1:0] HPTWReadPTE, // page table entry from LSU
|
input logic [`XLEN-1:0] HPTWReadPTE, // page table entry from LSU
|
||||||
input logic HPTWStall, // stall from LSU
|
input logic DCacheStall, // stall from LSU
|
||||||
input logic MemAfterIWalkDone,
|
input logic MemAfterIWalkDone,
|
||||||
input logic AnyCPUReqM,
|
input logic AnyCPUReqM,
|
||||||
output logic [`XLEN-1:0] PTE, // page table entry to TLBs
|
output logic [`XLEN-1:0] PTE, // page table entry to TLBs
|
||||||
output logic [1:0] PageType, // page type to TLBs
|
output logic [1:0] PageType, // page type to TLBs
|
||||||
output logic ITLBWriteF, DTLBWriteM, // write TLB with new entry
|
output logic ITLBWriteF, DTLBWriteM, // write TLB with new entry
|
||||||
output logic SelPTW, // LSU Arbiter should select signals from the PTW rather than from the IEU
|
output logic HPTWStall,
|
||||||
output logic [`PA_BITS-1:0] TranslationPAdr,
|
output logic [`PA_BITS-1:0] TranslationPAdr,
|
||||||
output logic HPTWRead, // HPTW requesting to read memory
|
output logic HPTWRead, // HPTW requesting to read memory
|
||||||
output logic WalkerInstrPageFaultF, WalkerLoadPageFaultM,WalkerStorePageFaultM // faults
|
output logic WalkerInstrPageFaultF, WalkerLoadPageFaultM,WalkerStorePageFaultM // faults
|
||||||
@ -54,7 +54,7 @@ module hptw
|
|||||||
L1_ADR, L1_RD,
|
L1_ADR, L1_RD,
|
||||||
L2_ADR, L2_RD,
|
L2_ADR, L2_RD,
|
||||||
L3_ADR, L3_RD,
|
L3_ADR, L3_RD,
|
||||||
LEAF, IDLE, FAULT} statetype; // *** placed outside generate statement to remove synthesis errors
|
LEAF, LEAF_DELAY, IDLE, FAULT} statetype; // *** placed outside generate statement to remove synthesis errors
|
||||||
|
|
||||||
generate
|
generate
|
||||||
if (`MEM_VIRTMEM) begin
|
if (`MEM_VIRTMEM) begin
|
||||||
@ -81,12 +81,12 @@ module hptw
|
|||||||
assign TLBMiss = (DTLBMissM | ITLBMissF);
|
assign TLBMiss = (DTLBMissM | ITLBMissF);
|
||||||
|
|
||||||
// Determine which address to translate
|
// Determine which address to translate
|
||||||
assign TranslationVAdr = DTLBWalk ? MemAdrM : PCF;
|
assign TranslationVAdr = DTLBWalk ? IEUAdrM : PCF;
|
||||||
assign CurrentPPN = PTE[`PPN_BITS+9:10];
|
assign CurrentPPN = PTE[`PPN_BITS+9:10];
|
||||||
|
|
||||||
// State flops
|
// State flops
|
||||||
flopenr #(1) TLBMissMReg(clk, reset, StartWalk, DTLBMissM, DTLBWalk); // when walk begins, record whether it was for DTLB (or record 0 for ITLB)
|
flopenr #(1) TLBMissMReg(clk, reset, StartWalk, DTLBMissM, DTLBWalk); // when walk begins, record whether it was for DTLB (or record 0 for ITLB)
|
||||||
assign PRegEn = HPTWRead & ~HPTWStall;
|
assign PRegEn = HPTWRead & ~DCacheStall;
|
||||||
flopenr #(`XLEN) PTEReg(clk, reset, PRegEn, HPTWReadPTE, PTE); // Capture page table entry from data cache
|
flopenr #(`XLEN) PTEReg(clk, reset, PRegEn, HPTWReadPTE, PTE); // Capture page table entry from data cache
|
||||||
|
|
||||||
// Assign PTE descriptors common across all XLEN values
|
// Assign PTE descriptors common across all XLEN values
|
||||||
@ -100,7 +100,7 @@ module hptw
|
|||||||
// Enable and select signals based on states
|
// Enable and select signals based on states
|
||||||
assign StartWalk = (WalkerState == IDLE) & TLBMiss;
|
assign StartWalk = (WalkerState == IDLE) & TLBMiss;
|
||||||
assign HPTWRead = (WalkerState == L3_RD) | (WalkerState == L2_RD) | (WalkerState == L1_RD) | (WalkerState == L0_RD);
|
assign HPTWRead = (WalkerState == L3_RD) | (WalkerState == L2_RD) | (WalkerState == L1_RD) | (WalkerState == L0_RD);
|
||||||
assign SelPTW = (WalkerState != IDLE) & (WalkerState != FAULT) & (WalkerState != LEAF);
|
assign HPTWStall = (WalkerState != IDLE) & (WalkerState != FAULT);
|
||||||
assign DTLBWriteM = (WalkerState == LEAF) & DTLBWalk;
|
assign DTLBWriteM = (WalkerState == LEAF) & DTLBWalk;
|
||||||
assign ITLBWriteF = (WalkerState == LEAF) & ~DTLBWalk;
|
assign ITLBWriteF = (WalkerState == LEAF) & ~DTLBWalk;
|
||||||
|
|
||||||
@ -168,7 +168,7 @@ module hptw
|
|||||||
IDLE: if (TLBMiss) NextWalkerState = InitialWalkerState;
|
IDLE: if (TLBMiss) NextWalkerState = InitialWalkerState;
|
||||||
else NextWalkerState = IDLE;
|
else NextWalkerState = IDLE;
|
||||||
L3_ADR: NextWalkerState = L3_RD; // first access in SV48
|
L3_ADR: NextWalkerState = L3_RD; // first access in SV48
|
||||||
L3_RD: if (HPTWStall) NextWalkerState = L3_RD;
|
L3_RD: if (DCacheStall) NextWalkerState = L3_RD;
|
||||||
else NextWalkerState = L2_ADR;
|
else NextWalkerState = L2_ADR;
|
||||||
// LEVEL3: if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF;
|
// LEVEL3: if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF;
|
||||||
// else if (ValidNonLeafPTE) NextWalkerState = L2_ADR;
|
// else if (ValidNonLeafPTE) NextWalkerState = L2_ADR;
|
||||||
@ -177,7 +177,7 @@ module hptw
|
|||||||
else if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages
|
else if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages
|
||||||
else if (ValidNonLeafPTE) NextWalkerState = L2_RD;
|
else if (ValidNonLeafPTE) NextWalkerState = L2_RD;
|
||||||
else NextWalkerState = FAULT;
|
else NextWalkerState = FAULT;
|
||||||
L2_RD: if (HPTWStall) NextWalkerState = L2_RD;
|
L2_RD: if (DCacheStall) NextWalkerState = L2_RD;
|
||||||
else NextWalkerState = L1_ADR;
|
else NextWalkerState = L1_ADR;
|
||||||
// LEVEL2: if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF;
|
// LEVEL2: if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF;
|
||||||
// else if (ValidNonLeafPTE) NextWalkerState = L1_ADR;
|
// else if (ValidNonLeafPTE) NextWalkerState = L1_ADR;
|
||||||
@ -186,7 +186,7 @@ module hptw
|
|||||||
else if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages
|
else if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages
|
||||||
else if (ValidNonLeafPTE) NextWalkerState = L1_RD;
|
else if (ValidNonLeafPTE) NextWalkerState = L1_RD;
|
||||||
else NextWalkerState = FAULT;
|
else NextWalkerState = FAULT;
|
||||||
L1_RD: if (HPTWStall) NextWalkerState = L1_RD;
|
L1_RD: if (DCacheStall) NextWalkerState = L1_RD;
|
||||||
else NextWalkerState = L0_ADR;
|
else NextWalkerState = L0_ADR;
|
||||||
// LEVEL1: if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF;
|
// LEVEL1: if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF;
|
||||||
// else if (ValidNonLeafPTE) NextWalkerState = L0_ADR;
|
// else if (ValidNonLeafPTE) NextWalkerState = L0_ADR;
|
||||||
@ -194,11 +194,13 @@ module hptw
|
|||||||
L0_ADR: if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages
|
L0_ADR: if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages
|
||||||
else if (ValidNonLeafPTE) NextWalkerState = L0_RD;
|
else if (ValidNonLeafPTE) NextWalkerState = L0_RD;
|
||||||
else NextWalkerState = FAULT;
|
else NextWalkerState = FAULT;
|
||||||
L0_RD: if (HPTWStall) NextWalkerState = L0_RD;
|
L0_RD: if (DCacheStall) NextWalkerState = L0_RD;
|
||||||
else NextWalkerState = LEAF;
|
else NextWalkerState = LEAF;
|
||||||
// LEVEL0: if (ValidLeafPTE) NextWalkerState = LEAF;
|
// LEVEL0: if (ValidLeafPTE) NextWalkerState = LEAF;
|
||||||
// else NextWalkerState = FAULT;
|
// else NextWalkerState = FAULT;
|
||||||
LEAF: NextWalkerState = IDLE;
|
LEAF: if (DTLBWalk) NextWalkerState = IDLE; // updates TLB
|
||||||
|
else NextWalkerState = IDLE;
|
||||||
|
LEAF_DELAY: NextWalkerState = IDLE; // give time to allow address translation
|
||||||
FAULT: if (ITLBMissF & AnyCPUReqM & ~MemAfterIWalkDone) NextWalkerState = FAULT;
|
FAULT: if (ITLBMissF & AnyCPUReqM & ~MemAfterIWalkDone) NextWalkerState = FAULT;
|
||||||
else NextWalkerState = IDLE;
|
else NextWalkerState = IDLE;
|
||||||
default: begin
|
default: begin
|
||||||
@ -209,7 +211,7 @@ module hptw
|
|||||||
end
|
end
|
||||||
endcase
|
endcase
|
||||||
end else begin // No Virtual memory supported; tie HPTW outputs to 0
|
end else begin // No Virtual memory supported; tie HPTW outputs to 0
|
||||||
assign HPTWRead = 0; assign SelPTW = 0;
|
assign HPTWRead = 0;
|
||||||
assign WalkerInstrPageFaultF = 0; assign WalkerLoadPageFaultM = 0; assign WalkerStorePageFaultM = 0;
|
assign WalkerInstrPageFaultF = 0; assign WalkerLoadPageFaultM = 0; assign WalkerStorePageFaultM = 0;
|
||||||
assign TranslationPAdr = 0;
|
assign TranslationPAdr = 0;
|
||||||
end
|
end
|
||||||
|
|||||||
@ -56,7 +56,7 @@ module privileged (
|
|||||||
input logic StoreMisalignedFaultM,
|
input logic StoreMisalignedFaultM,
|
||||||
input logic TimerIntM, ExtIntM, SwIntM,
|
input logic TimerIntM, ExtIntM, SwIntM,
|
||||||
input logic [63:0] MTIME_CLINT, MTIMECMP_CLINT,
|
input logic [63:0] MTIME_CLINT, MTIMECMP_CLINT,
|
||||||
input logic [`XLEN-1:0] InstrMisalignedAdrM, MemAdrM,
|
input logic [`XLEN-1:0] InstrMisalignedAdrM, IEUAdrM,
|
||||||
input logic [4:0] SetFflagsM,
|
input logic [4:0] SetFflagsM,
|
||||||
|
|
||||||
// Trap signals from pmp/pma in mmu
|
// Trap signals from pmp/pma in mmu
|
||||||
@ -231,7 +231,7 @@ module privileged (
|
|||||||
.MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW,
|
.MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW,
|
||||||
.STATUS_MIE, .STATUS_SIE,
|
.STATUS_MIE, .STATUS_SIE,
|
||||||
.PCM,
|
.PCM,
|
||||||
.InstrMisalignedAdrM, .MemAdrM,
|
.InstrMisalignedAdrM, .IEUAdrM,
|
||||||
.InstrM,
|
.InstrM,
|
||||||
.InstrValidM, .CommittedM,
|
.InstrValidM, .CommittedM,
|
||||||
.TrapM, .MTrapM, .STrapM, .UTrapM, .RetM,
|
.TrapM, .MTrapM, .STrapM, .UTrapM, .RetM,
|
||||||
|
|||||||
@ -39,7 +39,7 @@ module trap (
|
|||||||
(* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW,
|
(* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW,
|
||||||
input logic STATUS_MIE, STATUS_SIE,
|
input logic STATUS_MIE, STATUS_SIE,
|
||||||
input logic [`XLEN-1:0] PCM,
|
input logic [`XLEN-1:0] PCM,
|
||||||
input logic [`XLEN-1:0] InstrMisalignedAdrM, MemAdrM,
|
input logic [`XLEN-1:0] InstrMisalignedAdrM, IEUAdrM,
|
||||||
input logic [31:0] InstrM,
|
input logic [31:0] InstrM,
|
||||||
input logic InstrValidM, CommittedM,
|
input logic InstrValidM, CommittedM,
|
||||||
output logic TrapM, MTrapM, STrapM, UTrapM, RetM,
|
output logic TrapM, MTrapM, STrapM, UTrapM, RetM,
|
||||||
@ -157,12 +157,12 @@ module trap (
|
|||||||
|
|
||||||
always_comb
|
always_comb
|
||||||
if (InstrMisalignedFaultM) NextFaultMtvalM = InstrMisalignedAdrM;
|
if (InstrMisalignedFaultM) NextFaultMtvalM = InstrMisalignedAdrM;
|
||||||
else if (LoadMisalignedFaultM) NextFaultMtvalM = MemAdrM;
|
else if (LoadMisalignedFaultM) NextFaultMtvalM = IEUAdrM;
|
||||||
else if (StoreMisalignedFaultM) NextFaultMtvalM = MemAdrM;
|
else if (StoreMisalignedFaultM) NextFaultMtvalM = IEUAdrM;
|
||||||
else if (BreakpointFaultM) NextFaultMtvalM = PCM;
|
else if (BreakpointFaultM) NextFaultMtvalM = PCM;
|
||||||
else if (InstrPageFaultM) NextFaultMtvalM = PCM;
|
else if (InstrPageFaultM) NextFaultMtvalM = PCM;
|
||||||
else if (LoadPageFaultM) NextFaultMtvalM = MemAdrM;
|
else if (LoadPageFaultM) NextFaultMtvalM = IEUAdrM;
|
||||||
else if (StorePageFaultM) NextFaultMtvalM = MemAdrM;
|
else if (StorePageFaultM) NextFaultMtvalM = IEUAdrM;
|
||||||
else if (IllegalInstrFaultM) NextFaultMtvalM = {{(`XLEN-32){1'b0}}, InstrM};
|
else if (IllegalInstrFaultM) NextFaultMtvalM = {{(`XLEN-32){1'b0}}, InstrM};
|
||||||
else NextFaultMtvalM = 0;
|
else NextFaultMtvalM = 0;
|
||||||
endmodule
|
endmodule
|
||||||
|
|||||||
@ -123,7 +123,7 @@ module wallypipelinedhart (
|
|||||||
logic [2:0] Funct3M;
|
logic [2:0] Funct3M;
|
||||||
logic [`XLEN-1:0] IEUAdrE;
|
logic [`XLEN-1:0] IEUAdrE;
|
||||||
(* mark_debug = "true" *) logic [`XLEN-1:0] WriteDataM;
|
(* mark_debug = "true" *) logic [`XLEN-1:0] WriteDataM;
|
||||||
(* mark_debug = "true" *) logic [`XLEN-1:0] MemAdrM;
|
(* mark_debug = "true" *) logic [`XLEN-1:0] IEUAdrM;
|
||||||
(* mark_debug = "true" *) logic [`XLEN-1:0] ReadDataM;
|
(* mark_debug = "true" *) logic [`XLEN-1:0] ReadDataM;
|
||||||
logic [`XLEN-1:0] ReadDataW;
|
logic [`XLEN-1:0] ReadDataW;
|
||||||
logic CommittedM;
|
logic CommittedM;
|
||||||
@ -244,7 +244,7 @@ module wallypipelinedhart (
|
|||||||
.CommittedM, .DCacheMiss, .DCacheAccess,
|
.CommittedM, .DCacheMiss, .DCacheAccess,
|
||||||
.SquashSCW,
|
.SquashSCW,
|
||||||
//.DataMisalignedM(DataMisalignedM),
|
//.DataMisalignedM(DataMisalignedM),
|
||||||
.IEUAdrE, .MemAdrM, .WriteDataM,
|
.IEUAdrE, .IEUAdrM, .WriteDataM,
|
||||||
.ReadDataM, .FlushDCacheM,
|
.ReadDataM, .FlushDCacheM,
|
||||||
// connected to ahb (all stay the same)
|
// connected to ahb (all stay the same)
|
||||||
.DCtoAHBPAdrM, .DCtoAHBReadM, .DCtoAHBWriteM, .DCfromAHBAck,
|
.DCtoAHBPAdrM, .DCtoAHBReadM, .DCtoAHBWriteM, .DCfromAHBAck,
|
||||||
@ -328,7 +328,7 @@ module wallypipelinedhart (
|
|||||||
.LoadMisalignedFaultM, .StoreMisalignedFaultM,
|
.LoadMisalignedFaultM, .StoreMisalignedFaultM,
|
||||||
.TimerIntM, .ExtIntM, .SwIntM,
|
.TimerIntM, .ExtIntM, .SwIntM,
|
||||||
.MTIME_CLINT, .MTIMECMP_CLINT,
|
.MTIME_CLINT, .MTIMECMP_CLINT,
|
||||||
.InstrMisalignedAdrM, .MemAdrM,
|
.InstrMisalignedAdrM, .IEUAdrM,
|
||||||
.SetFflagsM,
|
.SetFflagsM,
|
||||||
// Trap signals from pmp/pma in mmu
|
// Trap signals from pmp/pma in mmu
|
||||||
// *** do these need to be split up into one for dmem and one for ifu?
|
// *** do these need to be split up into one for dmem and one for ifu?
|
||||||
|
|||||||
@ -93,14 +93,14 @@ module testbench();
|
|||||||
logic [`XLEN-1:0] PCW;
|
logic [`XLEN-1:0] PCW;
|
||||||
logic [31:0] InstrW;
|
logic [31:0] InstrW;
|
||||||
logic InstrValidW;
|
logic InstrValidW;
|
||||||
logic [`XLEN-1:0] MemAdrW, WriteDataW;
|
logic [`XLEN-1:0] IEUAdrW, WriteDataW;
|
||||||
logic TrapW;
|
logic TrapW;
|
||||||
`define FLUSHW dut.hart.FlushW
|
`define FLUSHW dut.hart.FlushW
|
||||||
`define STALLW dut.hart.StallW
|
`define STALLW dut.hart.StallW
|
||||||
flopenrc #(`XLEN) PCWReg(clk, reset, `FLUSHW, ~`STALLW, dut.hart.ifu.PCM, PCW);
|
flopenrc #(`XLEN) PCWReg(clk, reset, `FLUSHW, ~`STALLW, dut.hart.ifu.PCM, PCW);
|
||||||
flopenr #(32) InstrWReg(clk, reset, ~`STALLW, `FLUSHW ? nop : dut.hart.ifu.InstrM, InstrW);
|
flopenr #(32) InstrWReg(clk, reset, ~`STALLW, `FLUSHW ? nop : dut.hart.ifu.InstrM, InstrW);
|
||||||
flopenrc #(1) controlregW(clk, reset, `FLUSHW, ~`STALLW, dut.hart.ieu.c.InstrValidM, InstrValidW);
|
flopenrc #(1) controlregW(clk, reset, `FLUSHW, ~`STALLW, dut.hart.ieu.c.InstrValidM, InstrValidW);
|
||||||
flopenrc #(`XLEN) MemAdrWReg(clk, reset, `FLUSHW, ~`STALLW, dut.hart.MemAdrM, MemAdrW);
|
flopenrc #(`XLEN) IEUAdrWReg(clk, reset, `FLUSHW, ~`STALLW, dut.hart.IEUAdrM, IEUAdrW);
|
||||||
flopenrc #(`XLEN) WriteDataWReg(clk, reset, `FLUSHW, ~`STALLW, dut.hart.WriteDataM, WriteDataW);
|
flopenrc #(`XLEN) WriteDataWReg(clk, reset, `FLUSHW, ~`STALLW, dut.hart.WriteDataM, WriteDataW);
|
||||||
flopenr #(1) TrapWReg(clk, reset, ~`STALLW, dut.hart.hzu.TrapM, TrapW);
|
flopenr #(1) TrapWReg(clk, reset, ~`STALLW, dut.hart.hzu.TrapM, TrapW);
|
||||||
|
|
||||||
@ -134,7 +134,7 @@ module testbench();
|
|||||||
string RegWrite``STAGE; \
|
string RegWrite``STAGE; \
|
||||||
integer ExpectedRegAdr``STAGE; \
|
integer ExpectedRegAdr``STAGE; \
|
||||||
logic [`XLEN-1:0] ExpectedRegValue``STAGE; \
|
logic [`XLEN-1:0] ExpectedRegValue``STAGE; \
|
||||||
logic [`XLEN-1:0] ExpectedMemAdr``STAGE, ExpectedMemReadData``STAGE, ExpectedMemWriteData``STAGE; \
|
logic [`XLEN-1:0] ExpectedIEUAdr``STAGE, ExpectedMemReadData``STAGE, ExpectedMemWriteData``STAGE; \
|
||||||
string ExpectedCSRArray``STAGE[10:0]; \
|
string ExpectedCSRArray``STAGE[10:0]; \
|
||||||
logic [`XLEN-1:0] ExpectedCSRArrayValue``STAGE[10:0];
|
logic [`XLEN-1:0] ExpectedCSRArrayValue``STAGE[10:0];
|
||||||
`DECLARE_TRACE_SCANNER_SIGNALS(E)
|
`DECLARE_TRACE_SCANNER_SIGNALS(E)
|
||||||
@ -155,7 +155,7 @@ module testbench();
|
|||||||
integer ExpectedRegAdrW;
|
integer ExpectedRegAdrW;
|
||||||
logic [`XLEN-1:0] ExpectedRegValueW;
|
logic [`XLEN-1:0] ExpectedRegValueW;
|
||||||
string MemOpW;
|
string MemOpW;
|
||||||
logic [`XLEN-1:0] ExpectedMemAdrW, ExpectedMemReadDataW, ExpectedMemWriteDataW;
|
logic [`XLEN-1:0] ExpectedIEUAdrW, ExpectedMemReadDataW, ExpectedMemWriteDataW;
|
||||||
integer NumCSRW;
|
integer NumCSRW;
|
||||||
string ExpectedCSRArrayW[10:0];
|
string ExpectedCSRArrayW[10:0];
|
||||||
logic [`XLEN-1:0] ExpectedCSRArrayValueW[10:0];
|
logic [`XLEN-1:0] ExpectedCSRArrayValueW[10:0];
|
||||||
@ -411,7 +411,7 @@ module testbench();
|
|||||||
// parse memory address, read data, and/or write data \
|
// parse memory address, read data, and/or write data \
|
||||||
end else if(ExpectedTokens``STAGE[MarkerIndex``STAGE].substr(0, 2) == "Mem") begin \
|
end else if(ExpectedTokens``STAGE[MarkerIndex``STAGE].substr(0, 2) == "Mem") begin \
|
||||||
MemOp``STAGE = ExpectedTokens``STAGE[MarkerIndex``STAGE]; \
|
MemOp``STAGE = ExpectedTokens``STAGE[MarkerIndex``STAGE]; \
|
||||||
matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE+1], "%x", ExpectedMemAdr``STAGE); \
|
matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE+1], "%x", ExpectedIEUAdr``STAGE); \
|
||||||
matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE+2], "%x", ExpectedMemWriteData``STAGE); \
|
matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE+2], "%x", ExpectedMemWriteData``STAGE); \
|
||||||
matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE+3], "%x", ExpectedMemReadData``STAGE); \
|
matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE+3], "%x", ExpectedMemReadData``STAGE); \
|
||||||
MarkerIndex``STAGE += 4; \
|
MarkerIndex``STAGE += 4; \
|
||||||
@ -509,7 +509,7 @@ module testbench();
|
|||||||
RegWriteW <= "";
|
RegWriteW <= "";
|
||||||
ExpectedRegAdrW <= '0;
|
ExpectedRegAdrW <= '0;
|
||||||
ExpectedRegValueW <= '0;
|
ExpectedRegValueW <= '0;
|
||||||
ExpectedMemAdrW <= '0;
|
ExpectedIEUAdrW <= '0;
|
||||||
MemOpW <= "";
|
MemOpW <= "";
|
||||||
ExpectedMemWriteDataW <= '0;
|
ExpectedMemWriteDataW <= '0;
|
||||||
ExpectedMemReadDataW <= '0;
|
ExpectedMemReadDataW <= '0;
|
||||||
@ -522,7 +522,7 @@ module testbench();
|
|||||||
RegWriteW <= "";
|
RegWriteW <= "";
|
||||||
ExpectedRegAdrW <= '0;
|
ExpectedRegAdrW <= '0;
|
||||||
ExpectedRegValueW <= '0;
|
ExpectedRegValueW <= '0;
|
||||||
ExpectedMemAdrW <= '0;
|
ExpectedIEUAdrW <= '0;
|
||||||
MemOpW <= "";
|
MemOpW <= "";
|
||||||
ExpectedMemWriteDataW <= '0;
|
ExpectedMemWriteDataW <= '0;
|
||||||
ExpectedMemReadDataW <= '0;
|
ExpectedMemReadDataW <= '0;
|
||||||
@ -534,7 +534,7 @@ module testbench();
|
|||||||
RegWriteW <= RegWriteM;
|
RegWriteW <= RegWriteM;
|
||||||
ExpectedRegAdrW <= ExpectedRegAdrM;
|
ExpectedRegAdrW <= ExpectedRegAdrM;
|
||||||
ExpectedRegValueW <= ExpectedRegValueM;
|
ExpectedRegValueW <= ExpectedRegValueM;
|
||||||
ExpectedMemAdrW <= ExpectedMemAdrM;
|
ExpectedIEUAdrW <= ExpectedIEUAdrM;
|
||||||
MemOpW <= MemOpM;
|
MemOpW <= MemOpM;
|
||||||
ExpectedMemWriteDataW <= ExpectedMemWriteDataM;
|
ExpectedMemWriteDataW <= ExpectedMemWriteDataM;
|
||||||
ExpectedMemReadDataW <= ExpectedMemReadDataM;
|
ExpectedMemReadDataW <= ExpectedMemReadDataM;
|
||||||
@ -551,7 +551,7 @@ module testbench();
|
|||||||
//$display("%tns, %d instrs: Releasing force of MTIME_CLINT.", $time, InstrCountW);
|
//$display("%tns, %d instrs: Releasing force of MTIME_CLINT.", $time, InstrCountW);
|
||||||
release dut.uncore.clint.clint.MTIME;
|
release dut.uncore.clint.clint.MTIME;
|
||||||
end
|
end
|
||||||
//if (ExpectedMemAdrM == 'h10000005) begin
|
//if (ExpectedIEUAdrM == 'h10000005) begin
|
||||||
//$display("%tns, %d instrs: releasing force of ReadDataM.", $time, InstrCountW);
|
//$display("%tns, %d instrs: releasing force of ReadDataM.", $time, InstrCountW);
|
||||||
//release dut.hart.ieu.dp.ReadDataM;
|
//release dut.hart.ieu.dp.ReadDataM;
|
||||||
//end
|
//end
|
||||||
@ -588,8 +588,8 @@ module testbench();
|
|||||||
`checkEQ(name, dut.hart.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW)
|
`checkEQ(name, dut.hart.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW)
|
||||||
end
|
end
|
||||||
if (MemOpW.substr(0,2) == "Mem") begin
|
if (MemOpW.substr(0,2) == "Mem") begin
|
||||||
if(`DEBUG_TRACE >= 4) $display("\tMemAdrW: %016x ? expected: %016x", MemAdrW, ExpectedMemAdrW);
|
if(`DEBUG_TRACE >= 4) $display("\tIEUAdrW: %016x ? expected: %016x", IEUAdrW, ExpectedIEUAdrW);
|
||||||
`checkEQ("MemAdrW",MemAdrW,ExpectedMemAdrW)
|
`checkEQ("IEUAdrW",IEUAdrW,ExpectedIEUAdrW)
|
||||||
if(MemOpW == "MemR" || MemOpW == "MemRW") begin
|
if(MemOpW == "MemR" || MemOpW == "MemRW") begin
|
||||||
if(`DEBUG_TRACE >= 4) $display("\tReadDataW: %016x ? expected: %016x", dut.hart.ieu.dp.ReadDataW, ExpectedMemReadDataW);
|
if(`DEBUG_TRACE >= 4) $display("\tReadDataW: %016x ? expected: %016x", dut.hart.ieu.dp.ReadDataW, ExpectedMemReadDataW);
|
||||||
`checkEQ("ReadDataW",dut.hart.ieu.dp.ReadDataW,ExpectedMemReadDataW)
|
`checkEQ("ReadDataW",dut.hart.ieu.dp.ReadDataW,ExpectedMemReadDataW)
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user