diff --git a/dvtestplan.md b/dvtestplan.md
new file mode 100644
index 000000000..3b469e3b2
--- /dev/null
+++ b/dvtestplan.md
@@ -0,0 +1,30 @@
+# core-v-wally Design Verification Test Plan
+
+This document outlines the test plan for the Wally rv64gc configuration to reach Technology Readiness Level 5.
+
+1. Pass riscv-arch-test
+2. Boot Linux
+3. FPU pass all TestFloat vectors
+4. Performance verification: Caches and branch predictor miss rates match independent simulation
+5. Directed tests
+	- Privileged unit: Chapter 5 test plan
+	- MMU: PMA, PMP, virtual memory: Chapter 8 test plan
+	- Peripherals: Chapter 16 test plan
+6. Random tests
+	- riscdv tests
+7. Coverage tests
+	- Directed tests to bring coverage up to 100%.  
+		- Statement, experssion, branch, condition, FSM coverage in Questa 
+		- Do not measure toggle coverage
+
+All tests operate correctly in lock-step with ImperasDV
+
+Open questions:
+1. How to define extent of riscdv random tests needed?
+2. What other directed tests?
+    PMP Tests
+    Virtual Memory Tests
+		How to define pipeline tests? 
+			Simple ones like use after load stall are not important.
+			Hard ones such as page table walker fault during data access while I$ access is pending are hard to articulate and code
+      Is there an example of a good directed pipeline test plan & implementation
diff --git a/sim/imperas.ic b/sim/imperas.ic
index 4c221f2af..2c1225760 100644
--- a/sim/imperas.ic
+++ b/sim/imperas.ic
@@ -10,6 +10,10 @@
 --override cpu/mimpid=0x100
 --override refRoot/cpu/tvec_align=64
 
+# bit manipulation
+--override cpu/add_implicit_Extensions=B 
+--override cpu/bitmanip_version=1.0.0
+
 #  clarify
 #--override refRoot/cpu/mtvec_sext=F
 
diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv
index 95ab43360..f90e42ce9 100644
--- a/src/mmu/hptw.sv
+++ b/src/mmu/hptw.sv
@@ -288,7 +288,7 @@ module hptw (
       default:                                                        NextWalkerState = IDLE; // should never be reached
     endcase // case (WalkerState)
 
-  assign IgnoreRequestTLB = WalkerState == IDLE & TLBMiss;
+  assign IgnoreRequestTLB = (WalkerState == IDLE & TLBMiss) | (LSUAccessFaultM); // RT : 05 April 2023 if hptw request has pmp/a fault suppress bus access.
   assign SelHPTW = WalkerState != IDLE;
   assign HPTWAccessFaultDelay = HPTWLoadAccessFaultDelay | HPTWStoreAmoAccessFaultDelay | HPTWInstrAccessFaultDelay;
   assign HPTWStall = (WalkerState != IDLE) | (WalkerState == IDLE & TLBMiss & ~(HPTWAccessFaultDelay));
diff --git a/testbench/testbench_imperas.sv b/testbench/testbench_imperas.sv
index 56ca763af..b6d22feaf 100644
--- a/testbench/testbench_imperas.sv
+++ b/testbench/testbench_imperas.sv
@@ -403,7 +403,7 @@ module DCacheFlushFSM
                            // these dirty bit selections would be needed if dirty is moved inside the tag array.
           //.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].dirty.DirtyMem.RAM[index]),
           //.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.RAM[index][`PA_BITS+tagstart]),
-          .data(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].word[cacheWord].CacheDataMem.RAM[index]),
+          .data(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].word[cacheWord].wordram.CacheDataMem.RAM[index]),
           .index(index),
           .cacheWord(cacheWord),
           .CacheData(CacheData[way][index][cacheWord]),