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cachefsm cleanup.
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parent
ca459a5915
commit
190d619940
2
pipelined/src/cache/cache.sv
vendored
2
pipelined/src/cache/cache.sv
vendored
@ -125,7 +125,6 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) (
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.WriteWordEnable(SRAMWordEnable),
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.WriteWordEnable(SRAMWordEnable),
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.TagWriteEnable(SRAMLineWayWriteEnable),
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.TagWriteEnable(SRAMLineWayWriteEnable),
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.WriteData(SRAMWriteData),
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.WriteData(SRAMWriteData),
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//.SetValid(SetValidWay), .ClearValid(ClearValidWay), .SetDirty(SetDirtyWay), .ClearDirty(ClearDirtyWay),
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.SetValid(SetValidWay), .ClearValid(ClearValidWay), .SetDirty(SetDirtyWay), .ClearDirty(ClearDirtyWay),
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.SetValid(SetValidWay), .ClearValid(ClearValidWay), .SetDirty(SetDirtyWay), .ClearDirty(ClearDirtyWay),
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.SelEvict, .Victim(VictimWay), .Flush(FlushWay),
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.SelEvict, .Victim(VictimWay), .Flush(FlushWay),
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.SelFlush,
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.SelFlush,
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@ -191,7 +190,6 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) (
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assign NextFlushWay = {FlushWay[NUMWAYS-2:0], FlushWay[NUMWAYS-1]};
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assign NextFlushWay = {FlushWay[NUMWAYS-2:0], FlushWay[NUMWAYS-1]};
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assign SelectedWay = SelFlush ? FlushWay : (SRAMLineWriteEnable ? VictimWay : WayHit);
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assign SelectedWay = SelFlush ? FlushWay : (SRAMLineWriteEnable ? VictimWay : WayHit);
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//assign SelectedWay = SelFlush ? FlushWay : VictimWay;
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assign SetValidWay = SetValid ? SelectedWay : '0;
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assign SetValidWay = SetValid ? SelectedWay : '0;
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assign ClearValidWay = ClearValid ? SelectedWay : '0;
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assign ClearValidWay = ClearValid ? SelectedWay : '0;
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assign SetDirtyWay = SetDirty ? SelectedWay : '0;
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assign SetDirtyWay = SetDirty ? SelectedWay : '0;
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