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Debugging bus interface.

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This commit is contained in:
David Harris 2021-02-10 01:43:54 -05:00
parent 2357f5513b
commit 183a2dcfb5
3 changed files with 7 additions and 3 deletions
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7
wally-pipelined/src/ebu/ahblite.sv
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@ -110,6 +110,7 @@ module ahblite (
if (MemReadM) NextAdrState = MEMREAD; if (MemReadM) NextAdrState = MEMREAD;
else if (MemWriteM) NextAdrState = MEMWRITE; else if (MemWriteM) NextAdrState = MEMWRITE;
else if (InstrReadF) NextAdrState = INSTRREAD; else if (InstrReadF) NextAdrState = INSTRREAD;
// else if (1) NextAdrState = INSTRREAD; // dm 2/9/2021 testing
else NextAdrState = IDLE; else NextAdrState = IDLE;
// Generate acknowledges based on bus state and ready // Generate acknowledges based on bus state and ready
@ -159,8 +160,10 @@ module ahblite (
else InstrState <= NextInstrState;*/ else InstrState <= NextInstrState;*/
assign NextInstrState = (InstrState == 0 && MemState == 0 && (~MemReadM && ~MemWriteM && InstrReadF)) || assign NextInstrState = (InstrState == 0 && MemState == 0 && (~MemReadM && ~MemWriteM && InstrReadF)) ||
(InstrState == 1 && ~InstrAckD) || (InstrState == 1 && ~InstrAckD) ||
(InstrState == 1 && ResolveBranchD); // dh 2/8/2021 fixing (InstrState == 1 && ResolveBranchD); // dh 2/8/2021 fixing; delete this later
/* assign NextInstrState = (InstrState == 0 && MemState == 0 && (~MemReadM && ~MemWriteM)) ||
(InstrState == 1 && ~InstrAckD); // *** removed InstrReadF above dh 2/9/20 */
assign InstrStall = NextInstrState | MemState | NextMemState; // *** check this, explain better assign InstrStall = NextInstrState | MemState | NextMemState; // *** check this, explain better
// temporarily turn off stalls and check it works // temporarily turn off stalls and check it works
//assign DataStall = 0; //assign DataStall = 0;

2
wally-pipelined/src/hazard/hazard.sv
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@ -61,7 +61,7 @@ module hazard(
assign StallDCause = LoadStallD; // stall in decode if instruction is a load dependent on previous assign StallDCause = LoadStallD; // stall in decode if instruction is a load dependent on previous
assign StallECause = 0; assign StallECause = 0;
assign StallMCause = 0; // sDataStall; // not yet used*** assign StallMCause = 0; // sDataStall; // not yet used***
assign StallWCause = DataStall; assign StallWCause = DataStall; // | InstrStall;
// Each stage stalls if the next stage is stalled or there is a cause to stall this stage. // Each stage stalls if the next stage is stalled or there is a cause to stall this stage.
assign StallF = StallD | StallFCause; assign StallF = StallD | StallFCause;

1
wally-pipelined/testbench/testbench-imperas.sv
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@ -75,6 +75,7 @@ string tests64iNOc[] = {
"rv64i/I-MISALIGN_JMP-01","2000" "rv64i/I-MISALIGN_JMP-01","2000"
}; };
string tests64i[] = '{ string tests64i[] = '{
"rv64i/I-ENDIANESS-01", "2010",
"rv64i/I-ADD-01", "3000", "rv64i/I-ADD-01", "3000",
"rv64i/I-ADDI-01", "3000", "rv64i/I-ADDI-01", "3000",
"rv64i/I-ADDIW-01", "3000", "rv64i/I-ADDIW-01", "3000",