diff --git a/wally-pipelined/config/rv32ic/wally-config.vh b/wally-pipelined/config/rv32ic/wally-config.vh index fa16fdb86..1016f81f4 100644 --- a/wally-pipelined/config/rv32ic/wally-config.vh +++ b/wally-pipelined/config/rv32ic/wally-config.vh @@ -85,7 +85,7 @@ // Test modes // Tie GPIO outputs back to inputs -`define GPIO_LOOPBACK_TEST 0 +`define GPIO_LOOPBACK_TEST 1 // Busybear special CSR config to match OVPSim `define OVPSIM_CSR_CONFIG 0 diff --git a/wally-pipelined/src/ebu/ahblite.sv b/wally-pipelined/src/ebu/ahblite.sv index 23ae2eb65..378a5c78e 100644 --- a/wally-pipelined/src/ebu/ahblite.sv +++ b/wally-pipelined/src/ebu/ahblite.sv @@ -31,7 +31,7 @@ `include "wally-config.vh" package ahbliteState; - typedef enum {IDLE, MEMREAD, MEMWRITE, INSTRREAD, INSTRREADC, ATOMICREAD, ATOMICWRITE, MMUTRANSLATE} statetype; + typedef enum {IDLE, MEMREAD, MEMWRITE, INSTRREAD, ATOMICREAD, ATOMICWRITE, MMUTRANSLATE} statetype; endpackage module ahblite ( @@ -127,7 +127,7 @@ module ahblite ( else if (InstrReadF) NextBusState = INSTRREAD; else NextBusState = IDLE; MEMREAD: if (~HREADY) NextBusState = MEMREAD; - else if (InstrReadF) NextBusState = INSTRREADC; + else if (InstrReadF) NextBusState = INSTRREAD; else NextBusState = IDLE; MEMWRITE: if (~HREADY) NextBusState = MEMWRITE; else if (InstrReadF) NextBusState = INSTRREAD; @@ -135,8 +135,6 @@ module ahblite ( INSTRREAD: if (~HREADY) NextBusState = INSTRREAD; else NextBusState = IDLE; // if (InstrReadF still high) - INSTRREADC: if (~HREADY) NextBusState = INSTRREADC; // "C" for "competing", meaning please don't mess up the memread in the W stage. - else NextBusState = IDLE; default: NextBusState = IDLE; endcase @@ -147,12 +145,12 @@ module ahblite ( (NextBusState == ATOMICREAD) || (NextBusState == ATOMICWRITE) || MMUStall); - assign #1 InstrStall = ((NextBusState == INSTRREAD) || (NextBusState == INSTRREADC) || - MMUStall); + //assign #1 InstrStall = ((NextBusState == INSTRREAD) || (NextBusState == INSTRREADC) || + // MMUStall); // Determine access type (important for determining whether to fault) assign Atomic = ((NextBusState == ATOMICREAD) || (NextBusState == ATOMICWRITE)); - assign Execute = ((NextBusState == INSTRREAD) || (NextBusState == INSTRREADC)); + assign Execute = ((NextBusState == INSTRREAD)); assign Write = ((NextBusState == MEMWRITE) || (NextBusState == ATOMICWRITE)); assign Read = ((NextBusState == MEMREAD) || (NextBusState == ATOMICREAD) || (NextBusState == MMUTRANSLATE)); @@ -187,7 +185,7 @@ module ahblite ( assign MMUReady = (BusState == MMUTRANSLATE && NextBusState == IDLE); assign InstrRData = HRDATA; - assign InstrAckF = (BusState == INSTRREAD) && (NextBusState != INSTRREAD) || (BusState == INSTRREADC) && (NextBusState != INSTRREADC); + assign InstrAckF = (BusState == INSTRREAD) && (NextBusState != INSTRREAD); assign MemAckW = (BusState == MEMREAD) && (NextBusState != MEMREAD) || (BusState == MEMWRITE) && (NextBusState != MEMWRITE) || ((BusState == ATOMICREAD) && (NextBusState != ATOMICREAD)) || ((BusState == ATOMICWRITE) && (NextBusState != ATOMICWRITE)); assign MMUReadPTE = HRDATA; diff --git a/wally-pipelined/src/uncore/gpio.sv b/wally-pipelined/src/uncore/gpio.sv index 97e9f2ea6..887ff74f0 100644 --- a/wally-pipelined/src/uncore/gpio.sv +++ b/wally-pipelined/src/uncore/gpio.sv @@ -82,23 +82,6 @@ module gpio ( // register access always_ff @(posedge HCLK, negedge HRESETn) begin - // reads - case(entry) - 8'h00: Dout <= #1 input_val; - 8'h04: Dout <= #1 input_en; - 8'h08: Dout <= #1 output_en; - 8'h0C: Dout <= #1 output_val; - 8'h18: Dout <= #1 rise_ie; - 8'h1C: Dout <= #1 rise_ip; - 8'h20: Dout <= #1 fall_ie; - 8'h24: Dout <= #1 fall_ip; - 8'h28: Dout <= #1 high_ie; - 8'h2C: Dout <= #1 high_ip; - 8'h30: Dout <= #1 low_ie; - 8'h34: Dout <= #1 low_ip; - 8'h40: Dout <= #1 0; // OUT_XOR reads as 0 - default: Dout <= #1 0; - endcase // writes if (~HRESETn) begin // asynch reset @@ -114,22 +97,57 @@ module gpio ( high_ip <= #1 0; low_ie <= #1 0; low_ip <= #1 0; - end else if (memwrite) - // According to FE310 spec: Once the interrupt is pending, it will remain set until a 1 is written to the *_ip register at that bit. - case(entryd) - 8'h04: input_en <= #1 Din; - 8'h08: output_en <= #1 Din; - 8'h0C: output_val <= #1 Din; - 8'h18: rise_ie <= #1 Din; - 8'h1C: rise_ip <= #1 rise_ip & ~Din; - 8'h20: fall_ie <= #1 Din; - 8'h24: fall_ip <= #1 fall_ip & ~Din; - 8'h28: high_ie <= #1 Din; - 8'h2C: high_ip <= #1 high_ip & ~Din; - 8'h30: low_ie <= #1 Din; - 8'h34: low_ip <= #1 low_ip & ~Din; - 8'h40: output_val <= #1 output_val ^ Din; // OUT_XOR + end else begin + // writes + if (memwrite) + // According to FE310 spec: Once the interrupt is pending, it will remain set until a 1 is written to the *_ip register at that bit. + /* verilator lint_off CASEINCOMPLETE */ + case(entryd) + 8'h04: input_en <= #1 Din; + 8'h08: output_en <= #1 Din; + 8'h0C: output_val <= #1 Din; + 8'h18: rise_ie <= #1 Din; + 8'h20: fall_ie <= #1 Din; + 8'h28: high_ie <= #1 Din; + 8'h30: low_ie <= #1 Din; + 8'h40: output_val <= #1 output_val ^ Din; // OUT_XOR + endcase + /* verilator lint_on CASEINCOMPLETE */ + // reads + case(entry) + 8'h00: Dout <= #1 input_val; + 8'h04: Dout <= #1 input_en; + 8'h08: Dout <= #1 output_en; + 8'h0C: Dout <= #1 output_val; + 8'h18: Dout <= #1 rise_ie; + 8'h1C: Dout <= #1 rise_ip; + 8'h20: Dout <= #1 fall_ie; + 8'h24: Dout <= #1 fall_ip; + 8'h28: Dout <= #1 high_ie; + 8'h2C: Dout <= #1 high_ip; + 8'h30: Dout <= #1 low_ie; + 8'h34: Dout <= #1 low_ip; + 8'h40: Dout <= #1 0; // OUT_XOR reads as 0 + default: Dout <= #1 0; endcase + // interrupts + if (memwrite && (entryd == 8'h1C)) + rise_ip <= rise_ip & ~Din | (input2d & ~input3d); + else + rise_ip <= rise_ip | (input2d & ~input3d); + if (memwrite && (entryd == 8'h24)) + fall_ip <= fall_ip & ~Din | (~input2d & input3d); + else + fall_ip <= fall_ip | (~input2d & input3d); + if (memwrite && (entryd == 8'h2C)) + high_ip <= high_ip & ~Din | input3d; + else + high_ip <= high_ip | input3d; + if (memwrite && (entryd == 8'h34)) + low_ip <= low_ip & ~Din | ~input3d; + else + low_ip <= low_ip | ~input3d; + end end // chip i/o @@ -147,25 +165,6 @@ module gpio ( assign GPIOPinsOut = output_val; assign GPIOPinsEn = output_en; - // interrupts - always_ff @(posedge HCLK) begin - if (memwrite && (entryd == 8'h1C)) - rise_ip <= rise_ip & ~Din | (input2d & ~input3d); - else - rise_ip <= rise_ip | (input2d & ~input3d); - if (memwrite && (entryd == 8'h24)) - fall_ip <= fall_ip & ~Din | (~input2d & input3d); - else - fall_ip <= fall_ip | (~input2d & input3d); - if (memwrite && (entryd == 8'h2C)) - high_ip <= high_ip & ~Din | input3d; - else - high_ip <= high_ip | input3d; - if (memwrite && (entryd == 8'h34)) - low_ip <= low_ip & ~Din | ~input3d; - else - low_ip <= low_ip | ~input3d; - end assign GPIOIntr = |{(rise_ip & rise_ie),(fall_ip & fall_ip),(high_ip & high_ie),(low_ip & low_ie)}; endmodule diff --git a/wally-pipelined/src/uncore/plic.sv b/wally-pipelined/src/uncore/plic.sv index c9395dafc..4ee4ffbac 100644 --- a/wally-pipelined/src/uncore/plic.sv +++ b/wally-pipelined/src/uncore/plic.sv @@ -106,42 +106,44 @@ module plic ( intThreshold <= #1 3'b0; intInProgress <= #1 {N{1'b0}}; // writing - end else if (memwrite) - casez(entryd) - 28'hc0000??: intPriority[entryd[7:2]] <= #1 Din[2:0]; - `ifdef PLIC_NUM_SRC_LT_32 - 28'hc002000: intEn[N:1] <= #1 Din[N:1]; - `endif - `ifndef PLIC_NUM_SRC_LT_32 - 28'hc002000: intEn[31:1] <= #1 Din[31:1]; - 28'hc002004: intEn[N:32] <= #1 Din[31:0]; - `endif - 28'hc200000: intThreshold[2:0] <= #1 Din[2:0]; - 28'hc200004: intInProgress <= #1 intInProgress & ~(1'b1 << (Din[5:0]-1)); // lower "InProgress" to signify completion - endcase - // reading - if (memread) - casez(entry) - 28'hc0000??: Dout <= #1 {{(`XLEN-3){1'b0}},intPriority[entry[7:2]]}; - `ifdef PLIC_NUM_SRC_LT_32 - 28'hc001000: Dout <= #1 {{(31-N){1'b0}},intPending[N:1],1'b0}; - 28'hc002000: Dout <= #1 {{(31-N){1'b0}},intEn[N:1],1'b0}; - `endif - `ifndef PLIC_NUM_SRC_LT_32 - 28'hc001000: Dout <= #1 {intPending[31:1],1'b0}; - 28'hc001004: Dout <= #1 {{(63-N){1'b0}},intPending[N:32]}; - 28'hc002000: Dout <= #1 {intEn[31:1],1'b0}; - 28'hc002004: Dout <= #1 {{(63-N){1'b0}},intEn[N:32]}; - `endif - 28'hc200000: Dout <= #1 {29'b0,intThreshold[2:0]}; - 28'hc200004: begin - Dout <= #1 {26'b0,intClaim}; - intInProgress <= #1 intInProgress | (1'b1 << (intClaim-1)); // claimed requests are currently in progress of being serviced until they are completed - end - default: Dout <= #1 32'hdeadbeef; // invalid access - endcase - else - Dout <= #1 32'h0; + end else begin + if (memwrite) + casez(entryd) + 28'hc0000??: intPriority[entryd[7:2]] <= #1 Din[2:0]; + `ifdef PLIC_NUM_SRC_LT_32 + 28'hc002000: intEn[N:1] <= #1 Din[N:1]; + `endif + `ifndef PLIC_NUM_SRC_LT_32 + 28'hc002000: intEn[31:1] <= #1 Din[31:1]; + 28'hc002004: intEn[N:32] <= #1 Din[31:0]; + `endif + 28'hc200000: intThreshold[2:0] <= #1 Din[2:0]; + 28'hc200004: intInProgress <= #1 intInProgress & ~(1'b1 << (Din[5:0]-1)); // lower "InProgress" to signify completion + endcase + // reading + if (memread) + casez(entry) + 28'hc0000??: Dout <= #1 {{(`XLEN-3){1'b0}},intPriority[entry[7:2]]}; + `ifdef PLIC_NUM_SRC_LT_32 + 28'hc001000: Dout <= #1 {{(31-N){1'b0}},intPending[N:1],1'b0}; + 28'hc002000: Dout <= #1 {{(31-N){1'b0}},intEn[N:1],1'b0}; + `endif + `ifndef PLIC_NUM_SRC_LT_32 + 28'hc001000: Dout <= #1 {intPending[31:1],1'b0}; + 28'hc001004: Dout <= #1 {{(63-N){1'b0}},intPending[N:32]}; + 28'hc002000: Dout <= #1 {intEn[31:1],1'b0}; + 28'hc002004: Dout <= #1 {{(63-N){1'b0}},intEn[N:32]}; + `endif + 28'hc200000: Dout <= #1 {29'b0,intThreshold[2:0]}; + 28'hc200004: begin + Dout <= #1 {26'b0,intClaim}; + intInProgress <= #1 intInProgress | (1'b1 << (intClaim-1)); // claimed requests are currently in progress of being serviced until they are completed + end + default: Dout <= #1 32'hdeadbeef; // invalid access + endcase + else + Dout <= #1 32'h0; + end end // connect sources to requests diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index f99ee1aff..6223edfc3 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -29,7 +29,7 @@ module testbench(); parameter DEBUG = 0; parameter TESTSBP = 0; - parameter TESTSPERIPH = 0; // set to 0 for regression + parameter TESTSPERIPH = 0 ; // set to 0 for regression logic clk; logic reset; @@ -425,7 +425,7 @@ module testbench(); if (TESTSPERIPH) begin tests = tests32periph; end else begin - tests = {tests32i, tests32p};//,tests32periph}; *** broken at the moment + tests = {tests32i, tests32p, tests32periph}; if (`C_SUPPORTED % 2 == 1) tests = {tests, tests32ic}; else tests = {tests, tests32iNOc}; if (`M_SUPPORTED % 2 == 1) tests = {tests, tests32m};