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ebu cleanup

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This commit is contained in:
David Harris 2023-01-14 19:19:34 -08:00
parent b4dd7b21e6
commit 17fd2d2a3b
5 changed files with 88 additions and 112 deletions
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2
pipelined/src/ebu/ahbcacheinterface.sv
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@ -98,6 +98,7 @@ module ahbcacheinterface #(parameter BEATSPERLINE, LINELEN, LOGWPL, CACHE_ENABLE
end end
assign CacheReadDataWordAHB = AHBWordSets[BeatCount[$clog2(LLENPOVERAHBW)-1:0]]; assign CacheReadDataWordAHB = AHBWordSets[BeatCount[$clog2(LLENPOVERAHBW)-1:0]];
end else assign CacheReadDataWordAHB = CacheReadDataWordM[`AHBW-1:0]; end else assign CacheReadDataWordAHB = CacheReadDataWordM[`AHBW-1:0];
mux2 #(`AHBW) HWDATAMux(.d0(CacheReadDataWordAHB), .d1(WriteDataM[`AHBW-1:0]), mux2 #(`AHBW) HWDATAMux(.d0(CacheReadDataWordAHB), .d1(WriteDataM[`AHBW-1:0]),
.s(~(CacheableOrFlushCacheM)), .y(PreHWDATA)); .s(~(CacheableOrFlushCacheM)), .y(PreHWDATA));
flopen #(`AHBW) wdreg(HCLK, HREADY, PreHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec flopen #(`AHBW) wdreg(HCLK, HREADY, PreHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec
@ -109,7 +110,6 @@ module ahbcacheinterface #(parameter BEATSPERLINE, LINELEN, LOGWPL, CACHE_ENABLE
flopen #(`AHBW/8) HWSTRBReg(HCLK, HREADY, BusByteMaskM[`AHBW/8-1:0], HWSTRB); flopen #(`AHBW/8) HWSTRBReg(HCLK, HREADY, BusByteMaskM[`AHBW/8-1:0], HWSTRB);
buscachefsm #(BeatCountThreshold, LOGWPL) AHBBuscachefsm( buscachefsm #(BeatCountThreshold, LOGWPL) AHBBuscachefsm(
.HCLK, .HRESETn, .Flush, .BusRW, .Stall, .BusCommitted, .BusStall, .CaptureEn, .SelBusBeat, .HCLK, .HRESETn, .Flush, .BusRW, .Stall, .BusCommitted, .BusStall, .CaptureEn, .SelBusBeat,
.CacheBusRW, .CacheBusAck, .BeatCount, .BeatCountDelayed, .CacheBusRW, .CacheBusAck, .BeatCount, .BeatCountDelayed,

12
pipelined/src/ebu/ahbinterface.sv
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@ -30,10 +30,8 @@
`include "wally-config.vh" `include "wally-config.vh"
module ahbinterface #(parameter LSU = 0) // **** modify to use LSU/ifu parameter to control widths of buses module ahbinterface #(parameter LSU = 0) ( // **** modify to use LSU/ifu parameter to control widths of buses
(
input logic HCLK, HRESETn, input logic HCLK, HRESETn,
// bus interface // bus interface
input logic HREADY, input logic HREADY,
input logic [`XLEN-1:0] HRDATA, input logic [`XLEN-1:0] HRDATA,
@ -50,17 +48,17 @@ module ahbinterface #(parameter LSU = 0) // **** modify to use LSU/ifu parameter
input logic Stall, input logic Stall,
output logic BusStall, output logic BusStall,
output logic BusCommitted, output logic BusCommitted,
output logic [(LSU ? `XLEN : 32)-1:0] FetchBuffer); output logic [(LSU ? `XLEN : 32)-1:0] FetchBuffer
);
logic CaptureEn; logic CaptureEn;
/// *** only 32 bit for IFU. localparam LEN = (LSU ? `XLEN : 32); // 32 bits for IFU, XLEN for LSU
localparam LEN = (LSU ? `XLEN : 32);
flopen #(LEN) fb(.clk(HCLK), .en(CaptureEn), .d(HRDATA[LEN-1:0]), .q(FetchBuffer)); flopen #(LEN) fb(.clk(HCLK), .en(CaptureEn), .d(HRDATA[LEN-1:0]), .q(FetchBuffer));
if(LSU) begin if(LSU) begin
// delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN // delay HWDATA by 1 cycle per spec; assumes AHBW = XLEN
flop #(`XLEN) wdreg(HCLK, WriteData, HWDATA); flop #(`XLEN) wdreg(HCLK, WriteData, HWDATA);
flop #(`XLEN/8) HWSTRBReg(HCLK, ByteMask, HWSTRB); flop #(`XLEN/8) HWSTRBReg(HCLK, ByteMask, HWSTRB);
end else begin end else begin

7
pipelined/src/ebu/amoalu.sv
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@ -32,13 +32,11 @@ module amoalu (
input logic [`XLEN-1:0] srca, srcb, input logic [`XLEN-1:0] srca, srcb,
input logic [6:0] funct, input logic [6:0] funct,
input logic [1:0] width, input logic [1:0] width,
output logic [`XLEN-1:0] result); output logic [`XLEN-1:0] result
);
logic [`XLEN-1:0] a, b, y; logic [`XLEN-1:0] a, b, y;
// *** can this be muxed into the regular ALU to avoid needing a second one? Only a good
// idea if the regular ALU is not the critical path
// *** see how synthesis generates this and optimize more structurally if necessary to share hardware // *** see how synthesis generates this and optimize more structurally if necessary to share hardware
// a single carry chain should be shared for + and the four min/max // a single carry chain should be shared for + and the four min/max
// and the same mux can be used to select b for swap. // and the same mux can be used to select b for swap.
@ -64,7 +62,6 @@ module amoalu (
end else begin:sext // `XLEN = 64 end else begin:sext // `XLEN = 64
always_comb always_comb
if (width == 2'b10) begin // sign-extend word-length operations if (width == 2'b10) begin // sign-extend word-length operations
// *** it would be more efficient to look at carry out of bit 31 to determine comparisons than do this big mux on and b
a = {{32{srca[31]}}, srca[31:0]}; a = {{32{srca[31]}}, srca[31:0]};
b = {{32{srcb[31]}}, srcb[31:0]}; b = {{32{srcb[31]}}, srcb[31:0]};
result = {{32{y[31]}}, y[31:0]}; result = {{32{y[31]}}, y[31:0]};

30
pipelined/src/ebu/buscachefsm.sv
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@ -28,8 +28,8 @@
`define BURST_EN 1 `define BURST_EN 1
// HCLK and clk must be the same clock! // HCLK and clk must be the same clock!
module buscachefsm #(parameter integer BeatCountThreshold, parameter integer LOGWPL) module buscachefsm #(parameter integer BeatCountThreshold, LOGWPL) (
(input logic HCLK, input logic HCLK,
input logic HRESETn, input logic HRESETn,
// IEU interface // IEU interface
@ -55,12 +55,7 @@ module buscachefsm #(parameter integer BeatCountThreshold, parameter integer LOG
output logic [2:0] HBURST output logic [2:0] HBURST
); );
typedef enum logic [2:0] {ADR_PHASE, typedef enum logic [2:0] {ADR_PHASE, DATA_PHASE, MEM3, CACHE_FETCH, CACHE_WRITEBACK} busstatetype;
DATA_PHASE,
MEM3,
CACHE_FETCH,
CACHE_WRITEBACK} busstatetype;
typedef enum logic [1:0] {AHB_IDLE = 2'b00, AHB_BUSY = 2'b01, AHB_NONSEQ = 2'b10, AHB_SEQ = 2'b11} ahbtranstype; typedef enum logic [1:0] {AHB_IDLE = 2'b00, AHB_BUSY = 2'b01, AHB_NONSEQ = 2'b10, AHB_SEQ = 2'b11} ahbtranstype;
(* mark_debug = "true" *) busstatetype CurrState, NextState; (* mark_debug = "true" *) busstatetype CurrState, NextState;
@ -78,7 +73,7 @@ module buscachefsm #(parameter integer BeatCountThreshold, parameter integer LOG
always_comb begin always_comb begin
case(CurrState) case(CurrState)
ADR_PHASE: if(HREADY & |BusRW) NextState = DATA_PHASE; ADR_PHASE: if (HREADY & |BusRW) NextState = DATA_PHASE;
else if (HREADY & CacheBusRW[0]) NextState = CACHE_WRITEBACK; else if (HREADY & CacheBusRW[0]) NextState = CACHE_WRITEBACK;
else if (HREADY & CacheBusRW[1]) NextState = CACHE_FETCH; else if (HREADY & CacheBusRW[1]) NextState = CACHE_FETCH;
else NextState = ADR_PHASE; else NextState = ADR_PHASE;
@ -99,20 +94,9 @@ module buscachefsm #(parameter integer BeatCountThreshold, parameter integer LOG
end end
// IEU, LSU, and IFU controls // IEU, LSU, and IFU controls
flopenr #(LOGWPL)
BeatCountReg(.clk(HCLK),
.reset(~HRESETn | BeatCntReset),
.en(BeatCntEn),
.d(NextBeatCount),
.q(BeatCount));
// Used to store data from data phase of AHB. // Used to store data from data phase of AHB.
flopenr #(LOGWPL) flopenr #(LOGWPL) BeatCountReg(HCLK, ~HRESETn | BeatCntReset, BeatCntEn, NextBeatCount, BeatCount);
BeatCountDelayedReg(.clk(HCLK), flopenr #(LOGWPL) BeatCountDelayedReg(HCLK, ~HRESETn | BeatCntReset, BeatCntEn, BeatCount, BeatCountDelayed);
.reset(~HRESETn | BeatCntReset),
.en(BeatCntEn),
.d(BeatCount),
.q(BeatCountDelayed));
assign NextBeatCount = BeatCount + 1'b1; assign NextBeatCount = BeatCount + 1'b1;
assign FinalBeatCount = BeatCountDelayed == BeatCountThreshold[LOGWPL-1:0]; assign FinalBeatCount = BeatCountDelayed == BeatCountThreshold[LOGWPL-1:0];
@ -124,7 +108,7 @@ module buscachefsm #(parameter integer BeatCountThreshold, parameter integer LOG
assign CacheAccess = CurrState == CACHE_FETCH | CurrState == CACHE_WRITEBACK; assign CacheAccess = CurrState == CACHE_FETCH | CurrState == CACHE_WRITEBACK;
assign BusStall = (CurrState == ADR_PHASE & (|BusRW | |CacheBusRW)) | assign BusStall = (CurrState == ADR_PHASE & (|BusRW | |CacheBusRW)) |
//(CurrState == DATA_PHASE & ~BusRW[0]) | // replace the next line with this. Fails uart test but i think it's a test problem not a hardware problem. //(CurrState == DATA_PHASE & ~BusRW[0]) | // *** replace the next line with this. Fails uart test but i think it's a test problem not a hardware problem.
(CurrState == DATA_PHASE) | (CurrState == DATA_PHASE) |
(CurrState == CACHE_FETCH & ~HREADY) | (CurrState == CACHE_FETCH & ~HREADY) |
(CurrState == CACHE_WRITEBACK & ~HREADY); (CurrState == CACHE_WRITEBACK & ~HREADY);

9
pipelined/src/ebu/busfsm.sv
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@ -27,8 +27,8 @@
`include "wally-config.vh" `include "wally-config.vh"
// HCLK and clk must be the same clock! // HCLK and clk must be the same clock!
module busfsm module busfsm (
(input logic HCLK, input logic HCLK,
input logic HRESETn, input logic HRESETn,
// IEU interface // IEU interface
@ -43,10 +43,7 @@ module busfsm
output logic HWRITE output logic HWRITE
); );
typedef enum logic [2:0] {ADR_PHASE, typedef enum logic [2:0] {ADR_PHASE, DATA_PHASE, MEM3} busstatetype;
DATA_PHASE,
MEM3} busstatetype;
typedef enum logic [1:0] {AHB_IDLE = 2'b00, AHB_BUSY = 2'b01, AHB_NONSEQ = 2'b10, AHB_SEQ = 2'b11} ahbtranstype; typedef enum logic [1:0] {AHB_IDLE = 2'b00, AHB_BUSY = 2'b01, AHB_NONSEQ = 2'b10, AHB_SEQ = 2'b11} ahbtranstype;
(* mark_debug = "true" *) busstatetype CurrState, NextState; (* mark_debug = "true" *) busstatetype CurrState, NextState;