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Fixed warnings of signed conversion and for Design Compiler

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This commit is contained in:
David Harris 2023-10-24 14:01:43 -07:00
parent 7fc5268f47
commit 17fd0c90da
4 changed files with 8 additions and 4 deletions
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2
src/ebu/ebufsmarb.sv
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@ -116,5 +116,5 @@ module ebufsmarb (
// 11 16 15 // 11 16 15
always_comb always_comb
if (HBURST[2:1] == 2'b00) Threshold = 4'b0000; if (HBURST[2:1] == 2'b00) Threshold = 4'b0000;
else Threshold = (2 << HBURST[2:1]) - 1; else Threshold = ('d2 << HBURST[2:1]) - 'd1;
endmodule endmodule

2
src/ifu/ifu.sv
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@ -389,7 +389,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
flopenrc #(1) CompressedDReg(clk, reset, FlushD, ~StallD, CompressedF, CompressedD); flopenrc #(1) CompressedDReg(clk, reset, FlushD, ~StallD, CompressedF, CompressedD);
flopenrc #(1) CompressedEReg(clk, reset, FlushE, ~StallE, CompressedD, CompressedE); flopenrc #(1) CompressedEReg(clk, reset, FlushE, ~StallE, CompressedD, CompressedE);
assign PCLinkE = PCE + (CompressedE ? 2 : 4); assign PCLinkE = PCE + (CompressedE ? 'd2 : 'd4); // 'd4 means 4 but stops Design Compiler complaining about signed to unsigned conversion
// pipeline original compressed instruction in case it is needed for MTVAL on an illegal instruction exception // pipeline original compressed instruction in case it is needed for MTVAL on an illegal instruction exception
flopenrc #(16) InstrRawEReg(clk, reset, FlushE, ~StallE, InstrRawD[15:0], InstrRawE); flopenrc #(16) InstrRawEReg(clk, reset, FlushE, ~StallE, InstrRawD[15:0], InstrRawE);

2
src/lsu/swbytemask.sv
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@ -33,7 +33,7 @@ module swbytemask #(parameter WORDLEN)(
output logic [WORDLEN/8-1:0] ByteMask output logic [WORDLEN/8-1:0] ByteMask
); );
assign ByteMask = ((2**(2**Size))-1) << Adr; assign ByteMask =(('d2**('d2**Size))-'d1) << Adr; // 'd2 means 2, but stops Design Compiler from complaining about signed to unsigned conversion
/* Equivalent to the following /* Equivalent to the following

6
synthDC/scripts/synth.tcl
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@ -12,6 +12,8 @@ suppress_message {VER-130}
# statements in initial blocks are ignored # statements in initial blocks are ignored
suppress_message {VER-281} suppress_message {VER-281}
suppress_message {VER-173} suppress_message {VER-173}
# Unsupported system task '$warn'
suppress_message {VER-274}
# Enable Multicore # Enable Multicore
set_host_options -max_cores $::env(MAXCORES) set_host_options -max_cores $::env(MAXCORES)
@ -107,6 +109,7 @@ if { $saifpower == 1 } {
if {$drive != "INV"} { if {$drive != "INV"} {
set_false_path -from [get_ports reset] set_false_path -from [get_ports reset]
} }
# for PPA multiplexer synthesis
if {(($::env(DESIGN) == "ppa_mux2d_1") || ($::env(DESIGN) == "ppa_mux4d_1") || ($::env(DESIGN) == "ppa_mux8d_1"))} { if {(($::env(DESIGN) == "ppa_mux2d_1") || ($::env(DESIGN) == "ppa_mux4d_1") || ($::env(DESIGN) == "ppa_mux8d_1"))} {
set_false_path -from {s} set_false_path -from {s}
} }
@ -124,12 +127,13 @@ if { $find_clock != [list] } {
set my_clk $my_clock_pin set my_clk $my_clock_pin
create_clock -period $my_period $my_clk create_clock -period $my_period $my_clk
set_clock_uncertainty $my_uncertainty [get_clocks $my_clk] set_clock_uncertainty $my_uncertainty [get_clocks $my_clk]
} else { } else {
echo "Did not find clock! Design is probably combinational!" echo "Did not find clock! Design is probably combinational!"
set my_clk vclk set my_clk vclk
create_clock -period $my_period -name $my_clk create_clock -period $my_period -name $my_clk
} }
# Optimize paths that are close to critical # Optimize paths that are close to critical
set_critical_range 0.05 $current_design set_critical_range 0.05 $current_design