From 179d321683365ab8802c1cbcbde40da803e11f56 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 29 Nov 2022 14:09:48 -0600 Subject: [PATCH] Cleaned up the wavefile and added logic to linearly populate the LRU before all ways are filled. --- pipelined/regression/wave.do | 46 +++++++++++---------------------- pipelined/src/cache/cache.sv | 6 ++--- pipelined/src/cache/cacheLRU.sv | 31 +++++++++++++++------- pipelined/src/cache/cacheway.sv | 14 +++++----- 4 files changed, 48 insertions(+), 49 deletions(-) diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do index 27cf500e7..02627cc79 100644 --- a/pipelined/regression/wave.do +++ b/pipelined/regression/wave.do @@ -248,18 +248,17 @@ add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/ add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CAdr add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay} add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cachereplacementpolicy/lru_enable_addr -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cachereplacementpolicy/HitWayEnc -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cachereplacementpolicy/LRUWriteEn -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cachereplacementpolicy/CAdr -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cachereplacementpolicy/ReplacementBits[0]} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cachereplacementpolicy/ReplacementBits -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cachereplacementpolicy/LineReplacementBits -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {replacement policy} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cachereplacementpolicy/ib[2]} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cachereplacementpolicy/VictimWay -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {replacement policy} -expand -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cachereplacementpolicy/ib -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cachereplacementpolicy/HitWayExpand -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cachereplacementpolicy/cEn +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CAdr +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {replacement policy} -expand -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/ +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded add wave -noupdate -expand -group lsu -expand -group dcache -group flush -radix unsigned /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirtyWay @@ -327,19 +326,19 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cach add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CAdr add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Valid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Valid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Valid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Valid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay @@ -626,21 +625,6 @@ add wave -noupdate /testbench/dut/core/lsu/LSURWM add wave -noupdate /testbench/dut/core/lsu/bus/dcache/CacheRWM add wave -noupdate /testbench/dut/core/lsu/CacheableM add wave -noupdate /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/IHAdrM -add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/vict/cachereplacementpolicy/HitWay -add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/vict/cachereplacementpolicy/HitWayEnc -add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/vict/cachereplacementpolicy/HitWayExpand -add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/vict/cachereplacementpolicy/NUMWAYS -add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/vict/cachereplacementpolicy/NUMLINES -add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/vict/cachereplacementpolicy/LOGNUMWAYS -add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/vict/cachereplacementpolicy/cEn -add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/vict/cachereplacementpolicy/LRUWriteEn -add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/vict/cachereplacementpolicy/HitWayExpand -add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/vict/cachereplacementpolicy/cEn -add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/vict/cachereplacementpolicy/NewReplacement -add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/vict/cachereplacementpolicy/ib -add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/vict/cachereplacementpolicy/VictimWayNew -add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/vict/cachereplacementpolicy/VictimWay -add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/vict/cachereplacementpolicy/HitWay TreeUpdate [SetDefaultTree] WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {313524 ns} 1} {{Cursor 4} {313364 ns} 1} {{Cursor 5} {311625 ns} 0} quietly wave cursor active 5 diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index fd9f9d0ed..4069d791f 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -75,7 +75,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE logic ClearValid; logic ClearDirty; logic [LINELEN-1:0] ReadDataLineWay [NUMWAYS-1:0]; - logic [NUMWAYS-1:0] HitWay; + logic [NUMWAYS-1:0] HitWay, ValidWay; logic CacheHit; logic SetDirty; logic SetValid; @@ -128,11 +128,11 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE cacheway #(NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN, DCACHE) CacheWays[NUMWAYS-1:0](.clk, .reset, .ce, .CAdr, .PAdr, .LineWriteData, .LineByteMask, .SetValidWay, .ClearValidWay, .SetDirtyWay, .ClearDirtyWay, .SelEvict, .VictimWay, - .FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .VictimDirtyWay, .VictimTagWay, .FlushStage, + .FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .ValidWay, .VictimDirtyWay, .VictimTagWay, .FlushStage, .Invalidate(InvalidateCache)); if(NUMWAYS > 1) begin:vict cacheLRU #(NUMWAYS, SETLEN, OFFSETLEN, NUMLINES) cacheLRU( - .clk, .reset, .ce, .HitWay, .VictimWay, .CAdr, .LRUWriteEn(LRUWriteEn & ~FlushStage), .SetValid); + .clk, .reset, .ce, .HitWay, .ValidWay, .VictimWay, .CAdr, .LRUWriteEn(LRUWriteEn & ~FlushStage), .SetValid); end else assign VictimWay = 1'b1; // one hot. assign CacheHit = | HitWay; assign VictimDirty = | VictimDirtyWay; diff --git a/pipelined/src/cache/cacheLRU.sv b/pipelined/src/cache/cacheLRU.sv index c5faf219c..d237db49b 100644 --- a/pipelined/src/cache/cacheLRU.sv +++ b/pipelined/src/cache/cacheLRU.sv @@ -34,27 +34,32 @@ module cacheLRU #(parameter NUMWAYS = 4, SETLEN = 9, OFFSETLEN = 5, NUMLINES = 128)( input logic clk, reset, ce, input logic [NUMWAYS-1:0] HitWay, + input logic [NUMWAYS-1:0] ValidWay, output logic [NUMWAYS-1:0] VictimWay, input logic [SETLEN-1:0] CAdr, input logic LRUWriteEn, SetValid); logic [NUMWAYS-2:0] LRUMemory [NUMLINES-1:0]; logic [NUMWAYS-2:0] CurrLRU; - logic [NUMWAYS-2:0] NewLRU; + logic [NUMWAYS-2:0] NextLRU; logic [NUMWAYS-1:0] Way; localparam LOGNUMWAYS = $clog2(NUMWAYS); logic [LOGNUMWAYS-1:0] WayEncoded; logic [NUMWAYS-2:0] WayExpanded; + logic AllValid; + genvar row; /* verilator lint_off UNOPTFLAT */ // Ross: For some reason verilator does not like this. I checked and it is not a circular path. - logic [NUMWAYS-2:0] MuxEnables; + logic [NUMWAYS-2:0] LRUUpdate; logic [LOGNUMWAYS-1:0] Intermediate [NUMWAYS-2:0]; /* verilator lint_on UNOPTFLAT */ + assign AllValid = &ValidWay; + ///// Update replacement bits. function integer log2 (integer value); for (log2=0; value>0; log2=log2+1) @@ -76,18 +81,18 @@ module cacheLRU end genvar r, a, s; - assign MuxEnables[NUMWAYS-2] = '1; + assign LRUUpdate[NUMWAYS-2] = '1; for(s = NUMWAYS-2; s >= NUMWAYS/2; s--) begin : enables localparam p = NUMWAYS - s - 1; localparam g = log2(p); localparam t0 = s - p; localparam t1 = t0 - 1; localparam r = LOGNUMWAYS - g; - assign MuxEnables[t0] = MuxEnables[s] & ~WayEncoded[r]; - assign MuxEnables[t1] = MuxEnables[s] & WayEncoded[r]; + assign LRUUpdate[t0] = LRUUpdate[s] & ~WayEncoded[r]; + assign LRUUpdate[t1] = LRUUpdate[s] & WayEncoded[r]; end - mux2 #(1) LRUMuxes[NUMWAYS-2:0](CurrLRU, ~WayExpanded, MuxEnables, NewLRU); + mux2 #(1) LRUMuxes[NUMWAYS-2:0](CurrLRU, ~WayExpanded, LRUUpdate, NextLRU); // Compute next victim way. for(s = NUMWAYS-2; s >= NUMWAYS/2; s--) begin @@ -101,15 +106,23 @@ module cacheLRU assign Intermediate[s] = CurrLRU[s] ? int1[LOGNUMWAYS-1:0] : int0[LOGNUMWAYS-1:0]; end - decoder #(LOGNUMWAYS) decoder (Intermediate[NUMWAYS-2], VictimWay); + logic [NUMWAYS-1:0] FirstZero; + logic [LOGNUMWAYS-1:0] FirstZeroWay; + logic [LOGNUMWAYS-1:0] VictimWayEnc; + + priorityonehot #(NUMWAYS) FirstZeroEncoder(~ValidWay, FirstZero); + binencoder #(NUMWAYS) FirstZeroWayEncoder(FirstZero, FirstZeroWay); + mux2 #(LOGNUMWAYS) VictimMux(FirstZeroWay, Intermediate[NUMWAYS-2], AllValid, VictimWayEnc); + //decoder #(LOGNUMWAYS) decoder (Intermediate[NUMWAYS-2], VictimWay); + decoder #(LOGNUMWAYS) decoder (VictimWayEnc, VictimWay); // LRU storage must be reset for modelsim to run. However the reset value does not actually matter in practice. always_ff @(posedge clk) begin if (reset) for (int set = 0; set < NUMLINES; set++) LRUMemory[set] <= '0; if(ce) begin if (LRUWriteEn) begin - LRUMemory[CAdr] <= NewLRU; - CurrLRU <= #1 NewLRU; + LRUMemory[CAdr] <= NextLRU; + CurrLRU <= #1 NextLRU; end else begin CurrLRU <= #1 LRUMemory[CAdr]; end diff --git a/pipelined/src/cache/cacheway.sv b/pipelined/src/cache/cacheway.sv index bd2b652c4..ed81c103b 100644 --- a/pipelined/src/cache/cacheway.sv +++ b/pipelined/src/cache/cacheway.sv @@ -54,6 +54,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, output logic [LINELEN-1:0] ReadDataLineWay, output logic HitWay, + output logic ValidWay, output logic VictimDirtyWay, output logic [TAGLEN-1:0] VictimTagWay); @@ -67,7 +68,6 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, logic [NUMLINES-1:0] DirtyBits; logic [LINELEN-1:0] ReadDataLine; logic [TAGLEN-1:0] ReadTag; - logic Valid; logic Dirty; logic SelData; logic SelTag; @@ -94,8 +94,8 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, // AND portion of distributed tag multiplexer mux2 #(1) seltagmux(VictimWay, FlushWay, SelFlush, SelTag); assign VictimTagWay = SelTag ? ReadTag : '0; // AND part of AOMux - assign VictimDirtyWay = SelTag & Dirty & Valid; - assign HitWay = Valid & (ReadTag == PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]); + assign VictimDirtyWay = SelTag & Dirty & ValidWay; + assign HitWay = ValidWay & (ReadTag == PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]); ///////////////////////////////////////////////////////////////////////////////////////////// // Data Array @@ -124,9 +124,11 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, ///////////////////////////////////////////////////////////////////////////////////////////// always_ff @(posedge clk) begin // Valid bit array, - if (reset | Invalidate) ValidBits <= #1 '0; - if(ce) begin Valid <= #1 ValidBits[CAdr]; - if (SetValidEN) ValidBits[CAdr] <= #1 1'b1; + if (reset) ValidBits <= #1 '0; + if(ce) begin + ValidWay <= #1 ValidBits[CAdr]; + if(Invalidate & ~FlushStage) ValidBits <= #1 '0; + else if (SetValidEN) ValidBits[CAdr] <= #1 1'b1; else if (ClearValidWay & ~FlushStage) ValidBits[CAdr] <= #1 1'b0; end end