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uncore: Revert changes to uncore.sv

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Previously I made changes to uncore.sv to enable external RAM with
the bsg_dmc memory controller. As it turns out, these changes were
unnecessary as I should have implemented the bsg_dmc interface at
the toplevel external AHB bus.
This commit is contained in:
Marcus Mellor 2024-02-29 10:35:39 -06:00
parent efc3bc9615
commit 1799823cf8
1 changed files with 13 additions and 23 deletions
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30
src/uncore/uncore.sv
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@ -63,17 +63,15 @@ module uncore import cvw::*; #(parameter cvw_t P)(
logic [P.XLEN-1:0] HREADRam, HREADSDC;
logic [12:0] HSELRegions;
logic [11:0] HSELRegions;
logic HSELDTIM, HSELIROM, HSELRam, HSELCLINT, HSELPLIC, HSELGPIO, HSELUART, HSELSPI;
logic HSELDTIMD, HSELIROMD, HSELEXTD, HSELRamD, HSELCLINTD, HSELPLICD, HSELGPIOD, HSELUARTD, HSELSDCD, HSELSPID;
logic HRESPRam, HRESPSDC;
logic HREADYRam, HRESPSDCD;
logic [P.XLEN-1:0] HREADBootRom;
logic HSELBootRom, HSELBootRomD, HRESPBootRom, HREADYBootRom, HREADYSDC;
logic [P.XLEN-1:0] HREADBsgDmc;
logic HSELBsgDmc, HSELBsgDmcD, HRESPBsgDmc, HREADYBsgDmc;
logic HSELNoneD;
logic UARTIntr, GPIOIntr, SPIIntr;
logic UARTIntr,GPIOIntr, SPIIntr;
logic SDCIntM;
logic PCLK, PRESETn, PWRITE, PENABLE;
@ -94,7 +92,7 @@ module uncore import cvw::*; #(parameter cvw_t P)(
adrdecs #(P) adrdecs(HADDR, 1'b1, 1'b1, 1'b1, HSIZE[1:0], HSELRegions);
// unswizzle HSEL signals
assign {HSELBsgDmc, HSELSPI, HSELEXTSDC, HSELPLIC, HSELUART, HSELGPIO, HSELCLINT, HSELRam, HSELBootRom, HSELEXT, HSELIROM, HSELDTIM} = HSELRegions[12:1];
assign {HSELSPI, HSELEXTSDC, HSELPLIC, HSELUART, HSELGPIO, HSELCLINT, HSELRam, HSELBootRom, HSELEXT, HSELIROM, HSELDTIM} = HSELRegions[11:1];
// AHB -> APB bridge
ahbapbbridge #(P, 5) ahbapbbridge (
@ -160,38 +158,30 @@ module uncore import cvw::*; #(parameter cvw_t P)(
assign SPIOut = 0; assign SPICS = 0; assign SPIIntr = 0;
end
// FIXME: Do we need to block this off in an if (like SPI above)?
bsg_dmc_ahb #(P.PA_BITS, P.XLEN) external_ram (
.HCLK, .HRESETn, .HSEL(HSELBsgDmc), .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HTRANS, .HREADY,
.HRDATA(HREADBsgDmc), .HRESP(HRESPBsgDmc), .HREADYOUT(HREADYBsgDmc));
// AHB Read Multiplexer
assign HRDATA = ({P.XLEN{HSELRamD}} & HREADRam) |
({P.XLEN{HSELEXTD | HSELEXTSDCD}} & HRDATAEXT) |
({P.XLEN{HSELBRIDGED}} & HREADBRIDGE) |
({P.XLEN{HSELBootRomD}} & HREADBootRom) |
({P.XLEN{HSELBsgDmcD}} & HREADBsgDmc);
({P.XLEN{HSELBootRomD}} & HREADBootRom);
assign HRESP = HSELRamD & HRESPRam |
(HSELEXTD | HSELEXTSDCD) & HRESPEXT |
HSELBRIDGE & HRESPBRIDGE |
HSELBootRomD & HRESPBootRom |
HSELBsgDmcD & HRESPBsgDmc;
HSELBootRomD & HRESPBootRom;
assign HREADY = HSELRamD & HREADYRam |
(HSELEXTD | HSELEXTSDCD) & HREADYEXT |
HSELBRIDGED & HREADYBRIDGE |
HSELBootRomD & HREADYBootRom |
HSELBsgDmcD & HREADYBsgDmc |
HSELNoneD; // don't lock up the bus if no region is being accessed
// Address Decoder Delay (figure 4-2 in spec)
// The select for HREADY needs to be based on the address phase address. If the device
// takes more than 1 cycle to repsond it needs to hold on to the old select until the
// device is ready. Hence this register must be selectively enabled by HREADY.
// However on reset None must be selected.
flopenl #(13) hseldelayreg(HCLK, ~HRESETn, HREADY, HSELRegions, 13'b1,
{HSELBsgDmcD, HSELSPID, HSELEXTSDCD, HSELPLICD, HSELUARTD, HSELGPIOD,
HSELCLINTD, HSELRamD, HSELBootRomD, HSELEXTD, HSELIROMD, HSELDTIMD, HSELNoneD});
// device is ready. Hense this register must be selectively enabled by HREADY.
// However on reset None must be seleted.
flopenl #(12) hseldelayreg(HCLK, ~HRESETn, HREADY, HSELRegions, 12'b1,
{HSELSPID, HSELEXTSDCD, HSELPLICD, HSELUARTD, HSELGPIOD, HSELCLINTD,
HSELRamD, HSELBootRomD, HSELEXTD, HSELIROMD, HSELDTIMD, HSELNoneD});
flopenr #(1) hselbridgedelayreg(HCLK, ~HRESETn, HREADY, HSELBRIDGE, HSELBRIDGED);
endmodule