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Improved RAS.

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This commit is contained in:
Ross Thompson 2023-01-25 17:06:25 -06:00
parent 56aa798d5c
commit 172c40d44b
5 changed files with 36 additions and 32 deletions
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7
pipelined/config/rv64gc/wally-config.vh
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@ -135,9 +135,10 @@
`define PLIC_UART_ID 10 `define PLIC_UART_ID 10
`define BPRED_ENABLED 1 `define BPRED_ENABLED 1
//`define BPTYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 `define BPTYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
`define BPTYPE "BPSPECULATIVEGLOBAL" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 //`define BPTYPE "BPSPECULATIVEGLOBAL" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
//`define BPTYPE "BPFOLDEDGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 //`define BPTYPE "BPGLOBAL" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
//`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2//`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
`define TESTSBP 0 `define TESTSBP 0
`define BPRED_SIZE 10 `define BPRED_SIZE 10

16
pipelined/src/ifu/brpred/RAsPredictor.sv
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@ -32,13 +32,10 @@ module RASPredictor
#(parameter int StackSize = 16 #(parameter int StackSize = 16
) )
(input logic clk, (input logic clk,
input logic reset, input logic reset, StallF, StallD, StallE,
input logic PopF,
output logic [`XLEN-1:0] RASPCF, output logic [`XLEN-1:0] RASPCF,
input logic [3:0] WrongPredInstrClassD, input logic [3:0] WrongPredInstrClassD,
input logic [3:0] InstrClassD, input logic [3:0] InstrClassD, InstrClassE, PredInstrClassF,
input logic PushE,
input logic incr,
input logic [`XLEN-1:0] PCLinkE input logic [`XLEN-1:0] PCLinkE
); );
@ -51,8 +48,15 @@ module RASPredictor
logic [Depth-1:0] PtrD, PtrQ, PtrP1, PtrM1; logic [Depth-1:0] PtrD, PtrQ, PtrP1, PtrM1;
logic [StackSize-1:0] [`XLEN-1:0] memory; logic [StackSize-1:0] [`XLEN-1:0] memory;
integer index; integer index;
logic PopF;
logic PushE;
assign CounterEn = PopF | PushE | incr | WrongPredInstrClassD[2];
assign PopF = PredInstrClassF[2] & ~StallF;
assign PushE = InstrClassE[3] & ~StallE;
assign CounterEn = PopF | PushE | WrongPredInstrClassD[2];
assign PtrD = PopF | InstrClassD[2] ? PtrM1 : PtrP1; assign PtrD = PopF | InstrClassD[2] ? PtrM1 : PtrP1;

21
pipelined/src/ifu/brpred/bpred.sv
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@ -99,7 +99,7 @@ module bpred (
end else if (`BPTYPE == "BPGSHARE") begin:Predictor end else if (`BPTYPE == "BPGSHARE") begin:Predictor
gshare DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, gshare DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
.PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE, .PCNextF, .PCE, .DirPredictionF, .DirPredictionWrongE,
.BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE); .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE);
end else if (`BPTYPE == "BPSPECULATIVEGSHARE") begin:Predictor end else if (`BPTYPE == "BPSPECULATIVEGSHARE") begin:Predictor
@ -147,15 +147,9 @@ module bpred (
// Part 3 RAS // Part 3 RAS
// *** need to add the logic to restore RAS on flushes. We will use incr for this. // *** need to add the logic to restore RAS on flushes. We will use incr for this.
// *** needs to include flushX // *** needs to include flushX
RASPredictor RASPredictor(.clk(clk), RASPredictor RASPredictor(.clk, .reset, .StallF, .StallD, .StallE,
.reset(reset), .PredInstrClassF, .InstrClassD, .InstrClassE,
.PopF(PredInstrClassF[2] & ~StallF), .WrongPredInstrClassD, .RASPCF, .PCLinkE);
.WrongPredInstrClassD,
.InstrClassD,
.RASPCF,
.PushE(InstrClassE[3] & ~StallE),
.incr(1'b0),
.PCLinkE);
assign BPPredPCF = PredInstrClassF[2] ? RASPCF : PredPCF; assign BPPredPCF = PredInstrClassF[2] ? RASPCF : PredPCF;
@ -228,4 +222,11 @@ module bpred (
// assign NextValidPCE = PCE; // assign NextValidPCE = PCE;
// end // end
// performance counters
// 1. class (class wrong / minstret)
// 2. target btb (btb target wrong / class[0,1,3]) (btb target wrong / (br + j + jal)
// 3. target ras (ras target wrong / class[2])
// 4. direction (br dir wrong / class[0])
endmodule endmodule

9
pipelined/src/ifu/brpred/globalhistory.sv
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@ -46,7 +46,7 @@ module globalhistory
logic [1:0] DirPredictionD, DirPredictionE; logic [1:0] DirPredictionD, DirPredictionE;
logic [1:0] NewDirPredictionE, NewDirPredictionM; logic [1:0] NewDirPredictionE, NewDirPredictionM;
logic [k-1:0] GHRF, GHRD, GHRE, GHRM, GHR; logic [k-1:0] GHRF, GHRD, GHRE, GHR;
logic [k-1:0] GHRNext; logic [k-1:0] GHRNext;
logic PCSrcM; logic PCSrcM;
@ -55,9 +55,9 @@ module globalhistory
.ce1(~StallF), .ce2(~StallM & ~FlushM), .ce1(~StallF), .ce2(~StallM & ~FlushM),
.ra1(GHR), .ra1(GHR),
.rd1(DirPredictionF), .rd1(DirPredictionF),
.wa2(GHRM), .wa2(GHRE),
.wd2(NewDirPredictionM), .wd2(NewDirPredictionE),
.we2(BranchInstrM & ~StallM & ~FlushM), .we2(BranchInstrE & ~StallM & ~FlushM),
.bwe2(1'b1)); .bwe2(1'b1));
flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, DirPredictionF, DirPredictionD); flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, DirPredictionF, DirPredictionD);
@ -76,7 +76,6 @@ module globalhistory
flopenrc #(k) GHRFReg(clk, reset, FlushD, ~StallF, GHR, GHRF); flopenrc #(k) GHRFReg(clk, reset, FlushD, ~StallF, GHR, GHRF);
flopenrc #(k) GHRDReg(clk, reset, FlushD, ~StallD, GHRF, GHRD); flopenrc #(k) GHRDReg(clk, reset, FlushD, ~StallD, GHRF, GHRD);
flopenrc #(k) GHREReg(clk, reset, FlushE, ~StallE, GHRD, GHRE); flopenrc #(k) GHREReg(clk, reset, FlushE, ~StallE, GHRD, GHRE);
flopenrc #(k) GHRMReg(clk, reset, FlushM, ~StallM, GHRE, GHRM);
endmodule endmodule

15
pipelined/src/ifu/brpred/gshare.sv
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@ -39,28 +39,28 @@ module gshare
output logic [1:0] DirPredictionF, output logic [1:0] DirPredictionF,
output logic DirPredictionWrongE, output logic DirPredictionWrongE,
// update // update
input logic [`XLEN-1:0] PCNextF, PCM, input logic [`XLEN-1:0] PCNextF, PCE,
input logic BranchInstrE, BranchInstrM, PCSrcE input logic BranchInstrE, BranchInstrM, PCSrcE
); );
logic [k-1:0] IndexNextF, IndexM; logic [k-1:0] IndexNextF, IndexE;
logic [1:0] DirPredictionD, DirPredictionE; logic [1:0] DirPredictionD, DirPredictionE;
logic [1:0] NewDirPredictionE, NewDirPredictionM; logic [1:0] NewDirPredictionE, NewDirPredictionM;
logic [k-1:0] GHRF, GHRD, GHRE, GHRM, GHR; logic [k-1:0] GHRF, GHRD, GHRE, GHR;
logic [k-1:0] GHRNext; logic [k-1:0] GHRNext;
logic PCSrcM; logic PCSrcM;
assign IndexNextF = GHR & {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]}; assign IndexNextF = GHR & {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
assign IndexM = GHRM & {PCM[k+1] ^ PCM[1], PCM[k:2]}; assign IndexE = GHRE & {PCE[k+1] ^ PCE[1], PCE[k:2]};
ram2p1r1wbe #(2**k, 2) PHT(.clk(clk), ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
.ce1(~StallF), .ce2(~StallM & ~FlushM), .ce1(~StallF), .ce2(~StallM & ~FlushM),
.ra1(IndexNextF), .ra1(IndexNextF),
.rd1(DirPredictionF), .rd1(DirPredictionF),
.wa2(IndexM), .wa2(IndexE),
.wd2(NewDirPredictionM), .wd2(NewDirPredictionE),
.we2(BranchInstrM & ~StallM & ~FlushM), .we2(BranchInstrE & ~StallM & ~FlushM),
.bwe2(1'b1)); .bwe2(1'b1));
flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, DirPredictionF, DirPredictionD); flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, DirPredictionF, DirPredictionD);
@ -78,7 +78,6 @@ module gshare
flopenrc #(k) GHRFReg(clk, reset, FlushD, ~StallF, GHR, GHRF); flopenrc #(k) GHRFReg(clk, reset, FlushD, ~StallF, GHR, GHRF);
flopenrc #(k) GHRDReg(clk, reset, FlushD, ~StallD, GHRF, GHRD); flopenrc #(k) GHRDReg(clk, reset, FlushD, ~StallD, GHRF, GHRD);
flopenrc #(k) GHREReg(clk, reset, FlushE, ~StallE, GHRD, GHRE); flopenrc #(k) GHREReg(clk, reset, FlushE, ~StallE, GHRD, GHRE);
flopenrc #(k) GHRMReg(clk, reset, FlushM, ~StallM, GHRE, GHRM);
endmodule endmodule