From 171430a695138cf4e0bac6f571da3705f09a8285 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 21 Jan 2024 14:41:22 -0800 Subject: [PATCH] FPU and PMP tests --- sim/coverage-exclusions-rv64gc.do | 6 ++++++ src/fpu/fcmp.sv | 7 ++++--- src/mmu/pmpchecker.sv | 10 +++++----- testbench/tests.vh | 1 + tests/coverage/fpu.S | 3 +++ tests/coverage/pmpcbo.S | 31 +++++++++++++++++++++++++++++++ 6 files changed, 50 insertions(+), 8 deletions(-) create mode 100644 tests/coverage/pmpcbo.S diff --git a/sim/coverage-exclusions-rv64gc.do b/sim/coverage-exclusions-rv64gc.do index a7c2249bc..33d4ca5cc 100644 --- a/sim/coverage-exclusions-rv64gc.do +++ b/sim/coverage-exclusions-rv64gc.do @@ -237,6 +237,12 @@ coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line2 -item e coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line2 -item b 1 coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line2 -item s 1 +# IMMU PMP does not support CBO instructions +coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange [GetLineNum ../src/mmu/pmpchecker.sv "exclusion-tag: immu-pmpcbom"] +coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange [GetLineNum ../src/mmu/pmpchecker.sv "exclusion-tag: immu-pmpcboz"] +coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange [GetLineNum ../src/mmu/pmpchecker.sv "exclusion-tag: immu-pmpcboaccess"] +#coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange [GetLineNum ../src/mmu/pmpchecker.sv "exclusion-tag: immu-pmpstoreamoaccessfault"] + # No irom set line [GetLineNum ../src/ifu/ifu.sv "~ITLBMissF & ~CacheableF & ~SelIROM"] coverage exclude -scope /dut/core/ifu -linerange $line-$line -item c 1 -feccondrow 6 diff --git a/src/fpu/fcmp.sv b/src/fpu/fcmp.sv index e330f1fda..227676203 100755 --- a/src/fpu/fcmp.sv +++ b/src/fpu/fcmp.sv @@ -67,12 +67,13 @@ module fcmp import cvw::*; #(parameter cvw_t P) ( // LT/LE - signaling - sets invalid if NaN input // EQ - quiet - sets invalid if signaling NaN input always_comb begin - case (OpCtrl[2:0]) + casez (OpCtrl[2:0]) 3'b110: CmpNV = EitherSNaN; //min 3'b101: CmpNV = EitherSNaN; //max 3'b010: CmpNV = EitherSNaN; //equal - 3'b001: CmpNV = Zfa ? EitherSNaN : EitherNaN; // fltq / flt perform CompareQuietLess / CompareSignalingLess differing on when to set invalid - 3'b011: CmpNV = Zfa ? EitherSNaN : EitherNaN; // fleq / fle differ on when to set invalid + 3'b0?1: if (P.ZFA_SUPPORTED) + CmpNV = Zfa ? EitherSNaN : EitherNaN; // fltq,fleq / flt,fle perform CompareQuietLess / CompareSignalingLess differing on when to set invalid + else CmpNV = EitherNaN; // flt, fle default: CmpNV = 1'bx; endcase end diff --git a/src/mmu/pmpchecker.sv b/src/mmu/pmpchecker.sv index ef8c42aac..97cc6a18d 100644 --- a/src/mmu/pmpchecker.sv +++ b/src/mmu/pmpchecker.sv @@ -70,13 +70,13 @@ module pmpchecker import cvw::*; #(parameter cvw_t P) ( priorityonehot #(P.PMP_ENTRIES) pmppriority(.a(Match), .y(FirstMatch)); // combine the match signal from all the adress decoders to find the first one that matches. // Only enforce PMP checking for S and U modes or in Machine mode when L bit is set in selected region - assign EnforcePMP = (PrivilegeModeW != P.M_MODE) | (|(L & FirstMatch)); // *** switch to this logic when PMP is initialized for non-machine mode + assign EnforcePMP = (PrivilegeModeW != P.M_MODE) | (|(L & FirstMatch)); - assign PMPCBOMAccessFault = EnforcePMP & (|CMOpM[2:0]) & ~|((R|W) & FirstMatch) ; - assign PMPCBOZAccessFault = EnforcePMP & CMOpM[3] & ~|(W & FirstMatch) ; - assign PMPCMOAccessFault = PMPCBOZAccessFault | PMPCBOMAccessFault; + assign PMPCBOMAccessFault = EnforcePMP & (|CMOpM[2:0]) & ~|((R|W) & FirstMatch) ; // exclusion-tag: immu-pmpcbom + assign PMPCBOZAccessFault = EnforcePMP & CMOpM[3] & ~|(W & FirstMatch) ; // exclusion-tag: immu-pmpcboz + assign PMPCMOAccessFault = PMPCBOZAccessFault | PMPCBOMAccessFault; // exclusion-tag: immu-pmpcboaccess assign PMPInstrAccessFaultF = EnforcePMP & ExecuteAccessF & ~|(X & FirstMatch) ; - assign PMPStoreAmoAccessFaultM = (EnforcePMP & WriteAccessM & ~|(W & FirstMatch)) | PMPCMOAccessFault; + assign PMPStoreAmoAccessFaultM = (EnforcePMP & WriteAccessM & ~|(W & FirstMatch)) | PMPCMOAccessFault; // exclusion-tag: immu-pmpstoreamoaccessfault assign PMPLoadAccessFaultM = EnforcePMP & ReadAccessM & ~|(R & FirstMatch) ; endmodule diff --git a/testbench/tests.vh b/testbench/tests.vh index fecf4ebc9..efb0e6788 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -67,6 +67,7 @@ string tvpaths[] = '{ "pmpcfg1", "pmpcfg2", "pmppriority", + "pmpcbo", "pmpadrdecs" }; diff --git a/tests/coverage/fpu.S b/tests/coverage/fpu.S index 3bf4c5422..0a9d4b7c1 100644 --- a/tests/coverage/fpu.S +++ b/tests/coverage/fpu.S @@ -155,6 +155,9 @@ main: .word 0xF0007053 // illegal fmv (bad Funct3) .word 0x43007053 // illegal fcvt.d.* (bad Rs2D) .word 0x42207053 // illegal fcvt.d.* (bad Rs2D[1]) + .word 0xD5F00053 // illegal fcvt.h.* (bad Rs2D) + .word 0xC5F00053 // illegal fcvt.*.h (bad Rs2D) + .word 0x04000043 // illegal fmadd.h (h not supported) // Test divide by zero with rounding mode toward zero li t0, 1 diff --git a/tests/coverage/pmpcbo.S b/tests/coverage/pmpcbo.S new file mode 100644 index 000000000..2e7eab642 --- /dev/null +++ b/tests/coverage/pmpcbo.S @@ -0,0 +1,31 @@ +// pmpcbo.S +// David_Harris@hmc.edu 1/21/24 +// Cover PMP checks of cache management instructions + +#include "WALLY-init-lib.h" +main: + + # set up PMP so user and supervisor mode can access partial address space + li t0, 0x080F; +# li t0, 0x0808; + csrw pmpcfg0, t0 # configure PMP0 to TOR RWX and PMP1 to TOR no access + li t0, 0x2003FFFF + li t1, 0xFFFFFFFF + csrw pmpaddr0, t0 # configure PMP0 top of range to 0x800FFFFF to allow all 32-bit addresses + csrw pmpaddr1, t1 # configure PMP1 top of range to 0xFFFFFFFF to prohibit accesses above + + # enable cbo instructions + li t0, 0xF0 + csrw menvcfg, t0 + csrw senvcfg, t0 + + # switch to supervisor mode + li a0, 1 + ecall + + # cbo instructions to PMP-forbidded address + li a0, 0x81000000 # forbidden address + cbo.zero (a0) + cbo.inval (a0) + + j done \ No newline at end of file