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added new constraints for fpga.

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This commit is contained in:
Ross Thompson 2022-09-17 22:20:06 -05:00
parent cb34b7c98f
commit 16e10a4c5b
2 changed files with 201 additions and 98 deletions
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207
fpga/constraints/debug2.xdc
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86
fpga/src/fpgaTop.v
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@ -70,21 +70,21 @@ module fpgaTop
wire peripheral_aresetn; wire peripheral_aresetn;
wire mb_reset; wire mb_reset;
wire [`AHBW-1:0] HRDATAEXT;
wire HREADYEXT;
wire HRESPEXT;
wire HSELEXT;
wire HCLKOpen; wire HCLKOpen;
wire HRESETnOpen; wire HRESETnOpen;
wire [31:0] HADDR; (* mark_debug = "true" *) wire [`AHBW-1:0] HRDATAEXT;
wire [`AHBW-1:0] HWDATA; (* mark_debug = "true" *) wire HREADYEXT;
wire HWRITE; (* mark_debug = "true" *) wire HRESPEXT;
wire [2:0] HSIZE; (* mark_debug = "true" *) wire HSELEXT;
wire [2:0] HBURST; (* mark_debug = "true" *) wire [31:0] HADDR;
(* mark_debug = "true" *) wire [`AHBW-1:0] HWDATA;
(* mark_debug = "true" *) wire HWRITE;
(* mark_debug = "true" *) wire [2:0] HSIZE;
(* mark_debug = "true" *) wire [2:0] HBURST;
(* mark_debug = "true" *) wire [1:0] HTRANS;
(* mark_debug = "true" *) wire HREADY;
wire [3:0] HPROT; wire [3:0] HPROT;
wire [1:0] HTRANS;
wire HMASTLOCK; wire HMASTLOCK;
wire HREADY;
@ -94,41 +94,41 @@ module fpgaTop
wire SDCCmdOE; wire SDCCmdOE;
wire SDCCmdOut; wire SDCCmdOut;
wire [3:0] m_axi_awid; (* mark_debug = "true" *) wire [3:0] m_axi_awid;
wire [7:0] m_axi_awlen; (* mark_debug = "true" *) wire [7:0] m_axi_awlen;
wire [2:0] m_axi_awsize; (* mark_debug = "true" *) wire [2:0] m_axi_awsize;
wire [1:0] m_axi_awburst; (* mark_debug = "true" *) wire [1:0] m_axi_awburst;
wire [3:0] m_axi_awcache; (* mark_debug = "true" *) wire [3:0] m_axi_awcache;
wire [31:0] m_axi_awaddr; (* mark_debug = "true" *) wire [31:0] m_axi_awaddr;
wire [2:0] m_axi_awprot; wire [2:0] m_axi_awprot;
wire m_axi_awvalid; (* mark_debug = "true" *) wire m_axi_awvalid;
wire m_axi_awready; (* mark_debug = "true" *) wire m_axi_awready;
wire m_axi_awlock; (* mark_debug = "true" *) wire m_axi_awlock;
wire [63:0] m_axi_wdata; (* mark_debug = "true" *) wire [63:0] m_axi_wdata;
wire [7:0] m_axi_wstrb; (* mark_debug = "true" *) wire [7:0] m_axi_wstrb;
wire m_axi_wlast; (* mark_debug = "true" *) wire m_axi_wlast;
wire m_axi_wvalid; (* mark_debug = "true" *) wire m_axi_wvalid;
wire m_axi_wready; (* mark_debug = "true" *) wire m_axi_wready;
wire [3:0] m_axi_bid; (* mark_debug = "true" *) wire [3:0] m_axi_bid;
wire [1:0] m_axi_bresp; (* mark_debug = "true" *) wire [1:0] m_axi_bresp;
wire m_axi_bvalid; (* mark_debug = "true" *) wire m_axi_bvalid;
wire m_axi_bready; (* mark_debug = "true" *) wire m_axi_bready;
wire [3:0] m_axi_arid; (* mark_debug = "true" *) wire [3:0] m_axi_arid;
wire [7:0] m_axi_arlen; (* mark_debug = "true" *) wire [7:0] m_axi_arlen;
wire [2:0] m_axi_arsize; (* mark_debug = "true" *) wire [2:0] m_axi_arsize;
wire [1:0] m_axi_arburst; (* mark_debug = "true" *) wire [1:0] m_axi_arburst;
wire [2:0] m_axi_arprot; wire [2:0] m_axi_arprot;
wire [3:0] m_axi_arcache; (* mark_debug = "true" *) wire [3:0] m_axi_arcache;
wire m_axi_arvalid; (* mark_debug = "true" *) wire m_axi_arvalid;
wire [31:0] m_axi_araddr; (* mark_debug = "true" *) wire [31:0] m_axi_araddr;
wire m_axi_arlock; wire m_axi_arlock;
wire m_axi_arready; (* mark_debug = "true" *) wire m_axi_arready;
wire [3:0] m_axi_rid; (* mark_debug = "true" *) wire [3:0] m_axi_rid;
wire [63:0] m_axi_rdata; (* mark_debug = "true" *) wire [63:0] m_axi_rdata;
wire [1:0] m_axi_rresp; (* mark_debug = "true" *) wire [1:0] m_axi_rresp;
wire m_axi_rvalid; (* mark_debug = "true" *) wire m_axi_rvalid;
wire m_axi_rlast; (* mark_debug = "true" *) wire m_axi_rlast;
wire m_axi_rready; (* mark_debug = "true" *) wire m_axi_rready;
wire [3:0] BUS_axi_arregion; wire [3:0] BUS_axi_arregion;
wire [3:0] BUS_axi_arqos; wire [3:0] BUS_axi_arqos;