diff --git a/sim/Makefile b/sim/Makefile index 52f7efdcf..396f6aa9d 100644 --- a/sim/Makefile +++ b/sim/Makefile @@ -15,6 +15,8 @@ all: riscoftests memfiles coveragetests # Link Linux test vectors #cd ../tests/linux-testgen/linux-testvectors/;./tvLinker.sh +wally-riscv-arch-test: wallyriscoftests memfiles + coverage: #make -C ../tests/coverage --jobs #iter-elf.bash --cover --search ../tests/coverage @@ -49,6 +51,10 @@ clean: riscoftests: # Builds riscv-arch-test 64 and 32-bit versions and builds wally-riscv-arch-test 64 and 32-bit versions make -C ../tests/riscof/ + +wallyriscoftests: +# Builds riscv-arch-test 64 and 32-bit versions and builds wally-riscv-arch-test 64 and 32-bit versions + make -C ../tests/riscof/ wally-riscv-arch-test memfiles: make -f makefile-memfile wally-sim-files --jobs diff --git a/sim/imperas.ic b/sim/imperas.ic index 483666cca..77324e754 100644 --- a/sim/imperas.ic +++ b/sim/imperas.ic @@ -56,8 +56,8 @@ # Enable SVADU hardware update of A/D bits when menvcfg.ADUE=1 --override cpu/Svadu=T ---override cpu/updatePTEA=F ---override cpu/updatePTED=F +#--override cpu/updatePTEA=F +#--override cpu/updatePTED=F # THIS NEEDS FIXING to 16 diff --git a/src/mmu/tlb/tlb.sv b/src/mmu/tlb/tlb.sv index 2685c831f..674e8ef33 100644 --- a/src/mmu/tlb/tlb.sv +++ b/src/mmu/tlb/tlb.sv @@ -90,6 +90,7 @@ module tlb import cvw::*; #(parameter cvw_t P, logic Misaligned; logic MegapageMisaligned; logic PTE_N; // NAPOT page table entry + logic NAPOT4; // pte.ppn[3:0] = 1000, indicating 64 KiB continuous NAPOT region if(P.XLEN == 32) begin assign MegapageMisaligned = |(PPN[9:0]); // must have zero PPN0 @@ -105,10 +106,11 @@ module tlb import cvw::*; #(parameter cvw_t P, end assign VPN = VAdr[P.VPN_BITS+11:12]; + assign NAPOT4 = (PPN[3:0] == 4'b1000); // 64 KiB contiguous region with pte.napot_bits = 4 tlbcontrol #(P, ITLB) tlbcontrol(.SATP_MODE, .VAdr, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_ADUE, .PrivilegeModeW, .ReadAccess, .WriteAccess, .CMOp, .DisableTranslation, .TLBFlush, - .PTEAccessBits, .CAMHit, .Misaligned, + .PTEAccessBits, .CAMHit, .Misaligned, .NAPOT4, .TLBMiss, .TLBHit, .TLBPageFault, .UpdateDA, .SV39Mode, .Translate, .PTE_N, .PBMemoryType); diff --git a/src/mmu/tlb/tlbcontrol.sv b/src/mmu/tlb/tlbcontrol.sv index d5047d9b9..ac630bc4e 100644 --- a/src/mmu/tlb/tlbcontrol.sv +++ b/src/mmu/tlb/tlbcontrol.sv @@ -41,6 +41,7 @@ module tlbcontrol import cvw::*; #(parameter cvw_t P, ITLB = 0) ( input logic [11:0] PTEAccessBits, input logic CAMHit, input logic Misaligned, + input logic NAPOT4, // pte.ppn[3:0] = 1000, indicating 64 KiB continuous NAPOT region output logic TLBMiss, output logic TLBHit, output logic TLBPageFault, @@ -85,9 +86,9 @@ module tlbcontrol import cvw::*; #(parameter cvw_t P, ITLB = 0) ( // check if reserved, N, or PBMT bits are malformed w in RV64 assign BadPBMT = PTE_PBMT != 0 & (~(P.SVPBMT_SUPPORTED & ENVCFG_PBMTE) | - {PTE_X, PTE_W, PTE_R} == 3'b000) | PTE_PBMT == 3; // PBMT must be zero if not supported or for non-leaf PTEs; - assign BadNAPOT = PTE_N & ~P.SVNAPOT_SUPPORTED; // N must be be 0 if CVNAPOT is not supported - assign BadReserved = PTE_RESERVED; // Reserved bits must be zero + {PTE_X, PTE_W, PTE_R} == 3'b000) | PTE_PBMT == 3; // PBMT must be zero if not supported or for non-leaf PTEs; + assign BadNAPOT = PTE_N & (~P.SVNAPOT_SUPPORTED | ~NAPOT4); // N must be be 0 if CVNAPOT is not supported or not 64 KiB contiguous region + assign BadReserved = PTE_RESERVED; // Reserved bits must be zero // Check whether the access is allowed, page faulting if not. if (ITLB == 1) begin:itlb // Instruction TLB fault checking diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.reference_output index 320d3f9c4..ca5c4d38f 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.reference_output @@ -108,6 +108,10 @@ beef0aa0 # Test 11.3.1.3.7(b): check successful read/write when D=0 and SVADU=1 00000000 BEEF0660 # Test 11.3.1.3.9: NAPOT read 0550DEAD +0000000d # Test 11.3.1.3.9: page fault on malformed NAPOT PTE +00000000 +00000bad +00000000 0000000f # Test 11.3.1.3.10: PBMT; write page fault because menvcfg.PBMTE = 0 00000000 00000009 # ecall from going to M mode from S mode diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.S index 7681438b6..0c4786729 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.S @@ -86,22 +86,23 @@ test_cases: .8byte 0x0000000080018040, 0x20000000200800DF, write64_test# Vaddr 0x8000, Paddr = 0x80200000, PBMT = 1 .8byte 0x0000000080018048, 0x40000000200800DF, write64_test# Vaddr 0x9000, Paddr = 0x80200000, PMBT = 2 .8byte 0x0000000080018050, 0x60000000200800DF, write64_test# Vaddr 0xA000, Paddr = 0x80200000, PMBT = 3 -.8byte 0x0000000080018080, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT -.8byte 0x0000000080018088, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT -.8byte 0x0000000080018090, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT -.8byte 0x0000000080018098, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT -.8byte 0x00000000800180A0, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT -.8byte 0x00000000800180A8, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT -.8byte 0x00000000800180B0, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT -.8byte 0x00000000800180B8, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT -.8byte 0x00000000800180C0, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT -.8byte 0x00000000800180C8, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT -.8byte 0x00000000800180D0, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT -.8byte 0x00000000800180D8, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT -.8byte 0x00000000800180E0, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT -.8byte 0x00000000800180E8, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT -.8byte 0x00000000800180F0, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT -.8byte 0x00000000800180F8, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT +.8byte 0x0000000080018080, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT +.8byte 0x0000000080018088, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT +.8byte 0x0000000080018090, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT +.8byte 0x0000000080018098, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT +.8byte 0x00000000800180A0, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT +.8byte 0x00000000800180A8, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT +.8byte 0x00000000800180B0, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT +.8byte 0x00000000800180B8, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT +.8byte 0x00000000800180C0, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT +.8byte 0x00000000800180C8, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT +.8byte 0x00000000800180D0, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT +.8byte 0x00000000800180D8, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT +.8byte 0x00000000800180E0, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT +.8byte 0x00000000800180E8, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT +.8byte 0x00000000800180F0, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT +.8byte 0x00000000800180F8, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT +.8byte 0x0000000080018150, 0x80000000200800DF, write64_test# Vaddr 0x20000, Paddr = 0x80200000, NAPOT malformed with ppn[3] =0 # Level 0 page table B .8byte 0x0000000080016FF8, 0x00000000200804CF, write64_test# Vaddr 0xFFFFFFFFFFFFF000, Paddr 0x80201000 aligned kilopage @@ -208,7 +209,7 @@ test_cases: # Now set ADUE bit .8byte 0x0, 0x0, goto_m_mode # change to M mode, 0x9 written to output -.8byte 0x0, 0x2000000000000000, write_menvcfg # set menvcfg.ADUE = 1 +.8byte 0x0, 0x2000000000000000, write_menvcfg # set menvcfg.HADE = 1 .8byte 0x0, 0x0, goto_s_mode # change to S mode, 0xb written to output # Since SVADU is 1, there are no faults when A/D=0 @@ -226,6 +227,9 @@ test_cases: # test 11.3.1.3.9 NAPOT read .8byte 0x1A400, 0x0550DEADBEEF0660, read64_test # read from NAPOT 64 KiB page +# test 11.3.1.3.9 NAPOT read +.8byte 0x2A400, 0x0550DEADBEEF0660, read64_test # read from NAPOT 64 KiB page with malformed PTE should page fault + # test 11.3.1.3.10 PBMT checks .8byte 0x8040, 0x1212343456567878, write64_test # Write fault with PBMT when menvcfg.PBMTE = 0 .8byte 0x0, 0x0, goto_m_mode # change to M mode, 0x9 written to output